sim_tb_top.v

Xilinx DDR2存储器接口调试代码

         end
         else begin
             // if the memory part is component or unbuffered DIMM
             if ( `DATA_WIDTH%16 ) begin
               // for the memory part x16, if the data width is not multiple
               // of 16, memory models are instantiated for all data with x16
               // memory model and except for MSB data. For the MSB data
               // of 8 bits, all memory data, strobe and mask data signals are
               // replicated to make it as x16 part. For example if the design
               // is generated for data width of 72, memory model x16 parts
               // instantiated for 4 times with data ranging from 0 to 63.
               // For MSB data ranging from 64 to 71, one x16 memory model
               // by replicating the 8-bit data twice and similarly
               // the case with data mask and strobe.
                  for(i = 0; i < `DATA_WIDTH/16 ; i = i+1) begin
                     ddr2_model u_mem0
                       (
                        .ck       (ddr2_clk[i]),
                        .ck_n     (ddr2_clk_n[i]),
                        .cke      (ddr2_cke),
                        .cs_n     (ddr2_cs_n),
                        .ras_n    (ddr2_ras_n),
                        .cas_n    (ddr2_cas_n),
                        .we_n     (ddr2_we_n),
                        .dm_rdqs  (ddr2_dm[(2*(i+1))-1 : i*2]),
                        .ba       (ddr2_ba),
                        .addr     (ddr2_address),
                        .dq       (ddr2_dq[(16*(i+1))-1 : i*16]),
                        .dqs      (ddr2_dqs[(2*(i+1))-1 : i*2]),
                        .dqs_n    (ddr2_dqs_n[(2*(i+1))-1 : i*2]),
                        .rdqs_n   (),
                        .odt      (ddr2_odt)
                        );
                  end

                  ddr2_model u_mem1
                    (
                     .ck        (ddr2_clk[`CLK_WIDTH-1]),
                     .ck_n      (ddr2_clk_n[`CLK_WIDTH-1]),
                     .cke       (ddr2_cke),
                     .cs_n      (ddr2_cs_n),
                     .ras_n     (ddr2_ras_n),
                     .cas_n     (ddr2_cas_n),
                     .we_n      (ddr2_we_n),
                     .dm_rdqs   ({ddr2_dm[`DATA_MASK_WIDTH - 1],
                                  ddr2_dm[`DATA_MASK_WIDTH - 1]}),
                     .ba        (ddr2_ba),
                     .addr      (ddr2_address),
                     .dq        ({ddr2_dq[`DATA_WIDTH - 1 : `DATA_WIDTH - 8],
                                  ddr2_dq[`DATA_WIDTH - 1 : `DATA_WIDTH - 8]}),
                     .dqs       ({ddr2_dqs[`DATA_STROBE_WIDTH - 1],
                                  ddr2_dqs[`DATA_STROBE_WIDTH - 1]}),
                     .dqs_n     ({ddr2_dqs_n[`DATA_STROBE_WIDTH - 1],
                                  ddr2_dqs_n[`DATA_STROBE_WIDTH - 1]}),
                     .rdqs_n    (),
                     .odt       (ddr2_odt)
                     );
            end
            else begin
               // if the data width is multiple of 16
                  for(i = 0; i < `DATA_STROBE_WIDTH/2; i = i+1)
                  begin
                     ddr2_model u_mem0
                       (
                        .ck       (ddr2_clk[i]),
                        .ck_n     (ddr2_clk_n[i]),
                        .cke      (ddr2_cke),
                        .cs_n     (ddr2_cs_n),
                        .ras_n    (ddr2_ras_n),
                        .cas_n    (ddr2_cas_n),
                        .we_n     (ddr2_we_n),
                        .dm_rdqs  (ddr2_dm[(2*(i+1))-1 : i*2]),
                        .ba       (ddr2_ba),
                        .addr     (ddr2_address),
                        .dq       (ddr2_dq[(16*(i+1))-1 : i*16]),
                        .dqs      (ddr2_dqs[(2*(i+1))-1 : i*2]),
                        .dqs_n    (ddr2_dqs_n[(2*(i+1))-1 : i*2]),
                        .rdqs_n   (),
                        .odt      (ddr2_odt)
                        );
                  end
            end
         end

      end else
        if (DEVICE_WIDTH == 8) begin
           // if the memory part is x8
           if ( REG_ENABLE ) begin
              // if the memory part is Registered DIMM
                 for(i = 0; i < `DATA_WIDTH/`DATABITSPERSTROBE; i = i+1) begin
                    
                    ddr2_model u_mem0
                      (
                       .ck        (ddr2_clk[`CLK_WIDTH*i/`DATA_STROBE_WIDTH]),
                       .ck_n      (ddr2_clk_n[`CLK_WIDTH*i/`DATA_STROBE_WIDTH]),
                       .cke       (ddr2_cke_reg),
                       .cs_n      (ddr2_cs_n_reg),
                       .ras_n     (ddr2_ras_n_reg),
                       .cas_n     (ddr2_cas_n_reg),
                       .we_n      (ddr2_we_n_reg),
                       .dm_rdqs   (ddr2_dm[i]),
                       .ba        (ddr2_ba_reg),
                       .addr      (ddr2_address_reg),
                       .dq        (ddr2_dq[(8*(i+1))-1 : i*8]),
                       .dqs       (ddr2_dqs[i]),
                       .dqs_n     (ddr2_dqs_n[i]),
                       .rdqs_n    (),
                       .odt       (ddr2_odt_reg)
                       );
                 end
           end
           else begin
              // if the memory part is component or unbuffered DIMM
                 for(i = 0; i < `DATA_STROBE_WIDTH; i = i+1) begin
                    ddr2_model u_mem0
                      (
                       .ck        (ddr2_clk[i]),
                       .ck_n      (ddr2_clk_n[i]),
                       .cke       (ddr2_cke),
                       .cs_n      (ddr2_cs_n),
                       .ras_n     (ddr2_ras_n),
                       .cas_n     (ddr2_cas_n),
                       .we_n      (ddr2_we_n),
                       .dm_rdqs   (ddr2_dm[i]),
                       .ba        (ddr2_ba),
                       .addr      (ddr2_address),
                       .dq        (ddr2_dq[(8*(i+1))-1 : i*8]),
                       .dqs       (ddr2_dqs[i]),
                       .dqs_n     (ddr2_dqs_n[i]),
                       .rdqs_n    (),
                       .odt       (ddr2_odt)
                       );
                 end
           end

        end else
          if (DEVICE_WIDTH == 4) begin
             // if the memory part is x4
             if ( REG_ENABLE ) begin
                // if the memory part is Registered DIMM
                   for(i = 0; i < `DATA_STROBE_WIDTH; i = i+1) begin
                      
                      ddr2_model u_mem0
                        (
                         .ck      (ddr2_clk[`CLK_WIDTH*i/`DATA_STROBE_WIDTH]),
                         .ck_n    (ddr2_clk_n[`CLK_WIDTH*i/`DATA_STROBE_WIDTH]),
                         .cke     (ddr2_cke_reg),
                         .cs_n    (ddr2_cs_n_reg),
                         .ras_n   (ddr2_ras_n_reg),
                         .cas_n   (ddr2_cas_n_reg),
                         .we_n    (ddr2_we_n_reg),
                         .dm_rdqs (ddr2_dm[i/2]),
                         .ba      (ddr2_ba_reg),
                         .addr    (ddr2_address_reg),
                         .dq      (ddr2_dq[(4*(i+1))-1 : i*4]),
                         .dqs     (ddr2_dqs[i]),
                         .dqs_n   (ddr2_dqs_n[i]),
                         .rdqs_n  (),
                         .odt     (ddr2_odt_reg)
                         );
                   end
             end
             else begin
                // if the memory part is component or unbuffered DIMM
                   for(i = 0; i < `DATA_STROBE_WIDTH; i = i+1) begin
                      ddr2_model u_mem0
                        (
                         .ck      (ddr2_clk[i]),
                         .ck_n    (ddr2_clk_n[i]),
                         .cke     (ddr2_cke),
                         .cs_n    (ddr2_cs_n),
                         .ras_n   (ddr2_ras_n),
                         .cas_n   (ddr2_cas_n),
                         .we_n    (ddr2_we_n),
                         .dm_rdqs (ddr2_dm[i/2]),
                         .ba      (ddr2_ba),
                         .addr    (ddr2_address),
                         .dq      (ddr2_dq[(4*(i+1))-1 : i*4]),
                         .dqs     (ddr2_dqs[i]),
                         .dqs_n   (ddr2_dqs_n[i]),
                         .rdqs_n  (),
                         .odt     (ddr2_odt)
                         );
                   end
             end
          end
   endgenerate

// synthesizable test bench provided for wotb designs
   ddr2_32Mx32_test_bench_0 test_bench0
      (
       .auto_ref_req      (cntrl0_auto_ref_req),
       .fpga_clk          (cntrl0_clk_tb),
       .fpga_rst90        (cntrl0_sys_rst90_tb),
       .fpga_rst180       (cntrl0_sys_rst180_tb),
       .clk90             (cntrl0_clk90_tb),
       .burst_done        (cntrl0_burst_done),
       .init_done         (init_done),
       .ar_done           (cntrl0_ar_done),
       .u_ack             (cntrl0_user_cmd_ack),
       .u_data_val        (cntrl0_user_data_valid),
       .u_data_o          (cntrl0_user_output_data),
       .u_addr            (cntrl0_user_input_address),
       .u_cmd             (cntrl0_user_command_register),
       .u_data_i          (cntrl0_user_input_data),
       .u_data_m          (cntrl0_user_data_mask),
       .led_error_output  (error),
       .data_valid_out    (data_valid_out)
       );

endmodule // sim_tb_top