sim_tb_top.v

Xilinx DDR2存储器接口调试代码

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2007 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, Inc.
// All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : $Name: i+IP+131489 $
//  \   \        Application        : MIG
//  /   /        Filename           : sim_tb_top.v
// /___/   /\    Date Last Modified : $Date: 2007/09/21 15:23:17 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
//
// Device      : Spartan-3/3A/3A-DSP
// Design Name : DDR2 SDRAM
// Purpose     : This is the simulation testbench which is used to verify the
//               design. The basic clocks and resets to the interface are
//               generated here. This also connects the memory interface to the
//               memory model.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

`include "../rtl/ddr2_32Mx32_parameters_0.v"

module sim_tb_top;

   localparam DEVICE_WIDTH = 16; // Memory device data width
   localparam REG_ENABLE   = `REGISTERED; // registered addr/ctrl

   localparam real CLK_PERIOD_NS   = 8000.0 / 1000.0;
   localparam real TCYC_200        = 5.0;
   localparam real TPROP_DQS       = 0.00;
   localparam real TPROP_PCB_CTRL  = 0.00;
   localparam real TPROP_PCB_DATA  = 0.00;

   reg       sys_clk;
   wire      sys_clk_n;
   wire      sys_clk_p;
   reg       sys_rst_n;

   wire [`DATA_WIDTH-1:0]        #(TPROP_PCB_DATA) ddr2_dq;
   wire [`DATA_STROBE_WIDTH-1:0] #(TPROP_PCB_DATA) ddr2_dqs;
   wire [`DATA_STROBE_WIDTH-1:0] #(TPROP_PCB_DATA) ddr2_dqs_n;
   wire [`DATA_MASK_WIDTH-1:0]   #(TPROP_PCB_DATA) ddr2_dm;
   wire [`CLK_WIDTH-1:0]         #(TPROP_PCB_CTRL) ddr2_clk;
   wire [`CLK_WIDTH-1:0]         #(TPROP_PCB_CTRL) ddr2_clk_n;
   wire [`ROW_ADDRESS-1:0]       #(TPROP_PCB_CTRL) ddr2_address;
   wire [`BANK_ADDRESS-1:0]      #(TPROP_PCB_CTRL) ddr2_ba;
   wire				 #(TPROP_PCB_CTRL) ddr2_ras_n;
   wire				 #(TPROP_PCB_CTRL) ddr2_cas_n;
   wire				 #(TPROP_PCB_CTRL) ddr2_we_n;
   wire			         #(TPROP_PCB_CTRL) ddr2_cs_n;
   wire                          #(TPROP_PCB_CTRL) ddr2_cke;
   wire                          #(TPROP_PCB_CTRL) ddr2_odt;
   wire                          error;
   wire                          init_done;
   wire                          cntrl0_data_valid_out;
   wire				 rst_dqs_div_loop;
   wire                          ddr2_reset_n;
   reg  [`ROW_ADDRESS-1:0]       ddr2_address_reg;
   reg  [`BANK_ADDRESS-1:0]      ddr2_ba_reg;
   reg                           ddr2_cke_reg;
   reg                           ddr2_ras_n_reg;
   reg                           ddr2_cas_n_reg;
   reg                           ddr2_we_n_reg;
   reg                           ddr2_cs_n_reg;
   reg                           ddr2_odt_reg;

   wire  cntrl0_burst_done;
   wire  cntrl0_ar_done;                       
   wire  cntrl0_user_data_valid;               
   wire  cntrl0_auto_ref_req;                  
   wire  cntrl0_user_cmd_ack;                  
   wire  [2:0]cntrl0_user_command_register;    
   wire  cntrl0_clk_tb;                        
   wire  cntrl0_clk90_tb;                      
   wire  cntrl0_sys_rst_tb;                    
   wire  cntrl0_sys_rst90_tb;                  
   wire  cntrl0_sys_rst180_tb;                 
   wire  [((`DATA_MASK_WIDTH*2)-1):0]cntrl0_user_data_mask;           
   wire  [(2*`DATA_WIDTH)-1:0]cntrl0_user_output_data;        
   wire  [(2*`DATA_WIDTH)-1:0]cntrl0_user_input_data;         
   wire  [((`ROW_ADDRESS +
             `COL_AP_WIDTH + `BANK_ADDRESS)-1):0]cntrl0_user_input_address;      

   //***************************************************************************
   // Clock generation and reset
   //***************************************************************************

   initial
     sys_clk = 1'b0;
   always
     sys_clk = #(CLK_PERIOD_NS/2) ~sys_clk;

   assign                sys_clk_p = sys_clk;
   assign                sys_clk_n = ~sys_clk;


   initial begin
      sys_rst_n = 1'b0;
      #200;
      sys_rst_n = 1'b1;
   end

   //***************************************************************************
   // FPGA memory controller
   //***************************************************************************

   ddr2_32Mx32 u_mem_controller
     (
      .sys_clk                  (sys_clk_p),
      .sys_clkb                    (sys_clk_n),
      .reset_in_n                (sys_rst_n),
      .cntrl0_ddr2_ras_n         (ddr2_ras_n),
      .cntrl0_ddr2_cas_n         (ddr2_cas_n),
      .cntrl0_ddr2_we_n          (ddr2_we_n),
      .cntrl0_ddr2_cs_n          (ddr2_cs_n),
      .cntrl0_ddr2_cke           (ddr2_cke),
      .cntrl0_ddr2_odt           (ddr2_odt),
      .cntrl0_ddr2_dm            (ddr2_dm),
      .cntrl0_ddr2_dq            (ddr2_dq),
      .cntrl0_ddr2_dqs           (ddr2_dqs),
      .cntrl0_ddr2_dqs_n         (ddr2_dqs_n),
      .cntrl0_ddr2_ck            (ddr2_clk),
      .cntrl0_ddr2_ck_n          (ddr2_clk_n),
      .cntrl0_ddr2_ba            (ddr2_ba),
      .cntrl0_ddr2_a             (ddr2_address),
      
      .cntrl0_burst_done             (cntrl0_burst_done),
      .cntrl0_init_done              (init_done),      
      .cntrl0_ar_done                (cntrl0_ar_done),             
      .cntrl0_user_data_valid        (cntrl0_user_data_valid),             
      .cntrl0_auto_ref_req           (cntrl0_auto_ref_req),             
      .cntrl0_user_cmd_ack           (cntrl0_user_cmd_ack),             
      .cntrl0_user_command_register  (cntrl0_user_command_register),             
      .cntrl0_clk_tb                 (cntrl0_clk_tb),             
      .cntrl0_clk90_tb               (cntrl0_clk90_tb),             
      .cntrl0_sys_rst_tb             (cntrl0_sys_rst_tb),             
      .cntrl0_sys_rst90_tb           (cntrl0_sys_rst90_tb),             
      .cntrl0_sys_rst180_tb          (cntrl0_sys_rst180_tb),             
      .cntrl0_user_output_data       (cntrl0_user_output_data),             
      .cntrl0_user_input_data        (cntrl0_user_input_data),             
      .cntrl0_user_input_address     (cntrl0_user_input_address),             
	  
      .cntrl0_user_data_mask         (cntrl0_user_data_mask), 
      .cntrl0_rst_dqs_div_in     (rst_dqs_div_loop), 
      .cntrl0_rst_dqs_div_out    (rst_dqs_div_loop) 
      
      );

   // Since registered DIMM model is not available for Micron, all memory
   // address and control signals are registered by one clock cycle.
   // Generate registered data outputs
   always @( posedge ddr2_clk[0] ) begin
      if ( ddr2_reset_n == 1'b0 ) begin
         ddr2_ras_n_reg    <= 1'b1;
         ddr2_cas_n_reg    <= 1'b1;
         ddr2_we_n_reg     <= 1'b1;
         ddr2_cs_n_reg     <= 1'b1;
         ddr2_odt_reg      <= 1'b0;
      end
      else begin
         ddr2_address_reg  <= #(CLK_PERIOD_NS/2) ddr2_address;
         ddr2_ba_reg       <= #(CLK_PERIOD_NS/2) ddr2_ba;
         ddr2_ras_n_reg    <= #(CLK_PERIOD_NS/2) ddr2_ras_n;
         ddr2_cas_n_reg    <= #(CLK_PERIOD_NS/2) ddr2_cas_n;
         ddr2_we_n_reg     <= #(CLK_PERIOD_NS/2) ddr2_we_n;
         ddr2_cs_n_reg     <= #(CLK_PERIOD_NS/2) ddr2_cs_n;
         ddr2_odt_reg      <= #(CLK_PERIOD_NS/2) ddr2_odt;
      end
   end

   // to avoid tIS violations on CKE when reset is deasserted
   always @( posedge ddr2_clk_n[0] )
      if ( ddr2_reset_n == 1'b0 )
         ddr2_cke_reg      <= 1'b0;
      else
         ddr2_cke_reg      <= #(CLK_PERIOD_NS) ddr2_cke;

   //***************************************************************************
   // Memory model instances
   //***************************************************************************
   genvar i;
   generate
      if (DEVICE_WIDTH == 16) begin
         // if memory part is x16
         if ( REG_ENABLE ) begin
            // if the memory part is Registered DIMM
               for(i = 0; i < `DATA_STROBE_WIDTH/2; i = i+1) begin : gen_bytes
                  
                  ddr2_model u_mem0
                    (
                     .ck        (ddr2_clk[`CLK_WIDTH*i/`DATA_STROBE_WIDTH]),
                     .ck_n      (ddr2_clk_n[`CLK_WIDTH*i/`DATA_STROBE_WIDTH]),
                     .cke       (ddr2_cke_reg),
                     .cs_n      (ddr2_cs_n_reg),
                     .ras_n     (ddr2_ras_n_reg),
                     .cas_n     (ddr2_cas_n_reg),
                     .we_n      (ddr2_we_n_reg),
                     .dm_rdqs   (ddr2_dm[(2*(i+1))-1 : i*2]),
                     .ba        (ddr2_ba_reg),
                     .addr      (ddr2_address_reg),
                     .dq        (ddr2_dq[(16*(i+1))-1 : i*16]),
                     .dqs       (ddr2_dqs[(2*(i+1))-1 : i*2]),
                     .dqs_n     (ddr2_dqs_n[(2*(i+1))-1 : i*2]),
                     .rdqs_n    (),
                     .odt       (ddr2_odt_reg)
                     );
               end