ddr2_model_parameters.vh

Xilinx DDR2存储器接口调试代码

       parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
       parameter TRP              =   12500; // tRP    ps    Precharge command period
       parameter TXARDS           =       8; // tXARDS tCK   Exit low power active power down to a read command
       parameter CL_TIME          =   12500; // CL     ps    Minimum CAS Latency
   `else `ifdef sg25
       parameter TCK_MIN          =    2500; // tCK    ps    Minimum Clock Cycle Time
       parameter TJIT_PER         =     100; // tJIT(per)  ps Period JItter
       parameter TJIT_DUTY        =     100; // tJIT(duty) ps Half Period Jitter
       parameter TJIT_CC          =     200; // tJIT(cc)   ps Cycle to Cycle jitter
       parameter TERR_2PER        =     150; // tERR(nper) ps Accumulated Error (2-cycle)
       parameter TERR_3PER        =     175; // tERR(nper) ps Accumulated Error (3-cycle)
       parameter TERR_4PER        =     200; // tERR(nper) ps Accumulated Error (4-cycle)
       parameter TERR_5PER        =     200; // tERR(nper) ps Accumulated Error (5-cycle)
       parameter TERR_N1PER       =     300; // tERR(nper) ps Accumulated Error (6-10-cycle)
       parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
       parameter TQHS             =     300; // tQHS   ps    Data hold skew factor
       parameter TAC              =     400; // tAC    ps    DQ output access time from CK/CK#
       parameter TDS              =      50; // tDS    ps    DQ and DM input setup time relative to DQS
       parameter TDH              =     125; // tDH    ps    DQ and DM input hold time relative to DQS
       parameter TDQSCK           =     350; // tDQSCK ps    DQS output access time from CK/CK#
       parameter TDQSQ            =     200; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
       parameter TWPRE            =    0.35; // tWPRE  tCK   DQS Write Preamble
       parameter TIS              =     200; // tIS    ps    Input Setup Time
       parameter TIH              =     275; // tIH    ps    Input Hold Time
       parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
       parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
       parameter TWTR             =   10000; // tWTR   ps    Write to Read command delay
       parameter TRP              =   15000; // tRP    ps    Precharge command period
       parameter TXARDS           =       8; // tXARDS tCK   Exit low power active power down to a read command
       parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
   `else `ifdef sg3E
       parameter TCK_MIN          =    3000; // tCK    ps    Minimum Clock Cycle Time
       parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
       parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
       parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
       parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
       parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
       parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
       parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
       parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
       parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
       parameter TQHS             =     340; // tQHS   ps    Data hold skew factor
       parameter TAC              =     450; // tAC    ps    DQ output access time from CK/CK#
       parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
       parameter TDH              =     175; // tDH    ps    DQ and DM input hold time relative to DQS
       parameter TDQSCK           =     400; // tDQSCK ps    DQS output access time from CK/CK#
       parameter TDQSQ            =     240; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
       parameter TWPRE            =    0.35; // tWPRE  tCK   DQS Write Preamble
       parameter TIS              =     200; // tIS    ps    Input Setup Time
       parameter TIH              =     275; // tIH    ps    Input Hold Time
       parameter TRC              =   54000; // tRC    ps    Active to Active/Auto Refresh command time
       parameter TRCD             =   12000; // tRCD   ps    Active to Read/Write command time
       parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
       parameter TRP              =   12000; // tRP    ps    Precharge command period
       parameter TXARDS           =       7; // tXARDS tCK   Exit low power active power down to a read command
       parameter CL_TIME          =   12000; // CL     ps    Minimum CAS Latency
   `else `ifdef sg3
       parameter TCK_MIN          =    3000; // tCK    ps    Minimum Clock Cycle Time
       parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
       parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
       parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
       parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
       parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
       parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
       parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
       parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
       parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
       parameter TQHS             =     340; // tQHS   ps    Data hold skew factor
       parameter TAC              =     450; // tAC    ps    DQ output access time from CK/CK#
       parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
       parameter TDH              =     175; // tDH    ps    DQ and DM input hold time relative to DQS
       parameter TDQSCK           =     400; // tDQSCK ps    DQS output access time from CK/CK#
       parameter TDQSQ            =     240; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
       parameter TWPRE            =    0.35; // tWPRE  tCK   DQS Write Preamble
       parameter TIS              =     200; // tIS    ps    Input Setup Time
       parameter TIH              =     275; // tIH    ps    Input Hold Time
       parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
       parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
       parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
       parameter TRP              =   15000; // tRP    ps    Precharge command period
       parameter TXARDS           =       7; // tXARDS tCK   Exit low power active power down to a read command
       parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
   `else `ifdef sg37E
       parameter TCK_MIN          =    3750; // tCK    ps    Minimum Clock Cycle Time
       parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
       parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
       parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
       parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
       parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
       parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
       parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
       parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
       parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
       parameter TQHS             =     400; // tQHS   ps    Data hold skew factor
       parameter TAC              =     500; // tAC    ps    DQ output access time from CK/CK#
       parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
       parameter TDH              =     225; // tDH    ps    DQ and DM input hold time relative to DQS
       parameter TDQSCK           =     450; // tDQSCK ps    DQS output access time from CK/CK#
       parameter TDQSQ            =     300; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
       parameter TWPRE            =    0.25; // tWPRE  tCK   DQS Write Preamble
       parameter TIS              =     250; // tIS    ps    Input Setup Time
       parameter TIH              =     375; // tIH    ps    Input Hold Time
       parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
       parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
       parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
       parameter TRP              =   15000; // tRP    ps    Precharge command period
       parameter TXARDS           =       6; // tXARDS tCK   Exit low power active power down to a read command
       parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
   `else `define sg5E
       parameter TCK_MIN          =    5000; // tCK    ps    Minimum Clock Cycle Time
       parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
       parameter TJIT_DUTY        =     150; // tJIT(duty) ps Half Period Jitter
       parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
       parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
       parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
       parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
       parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
       parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
       parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
       parameter TQHS             =     450; // tQHS   ps    Data hold skew factor
       parameter TAC              =     600; // tAC    ps    DQ output access time from CK/CK#
       parameter TDS              =     150; // tDS    ps    DQ and DM input setup time relative to DQS
       parameter TDH              =     275; // tDH    ps    DQ and DM input hold time relative to DQS
       parameter TDQSCK           =     500; // tDQSCK ps    DQS output access time from CK/CK#
       parameter TDQSQ            =     350; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
       parameter TWPRE            =    0.25; // tWPRE  tCK   DQS Write Preamble
       parameter TIS              =     350; // tIS    ps    Input Setup Time
       parameter TIH              =     475; // tIH    ps    Input Hold Time
       parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
       parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
       parameter TWTR             =   10000; // tWTR   ps    Write to Read command delay
       parameter TRP              =   15000; // tRP    ps    Precharge command period
       parameter TXARDS           =       6; // tXARDS tCK   Exit low power active power down to a read command
       parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
   `endif `endif `endif `endif `endif

       // Timing Parameters

       // Mode Register
       parameter AL_MIN           =       0; // AL     tCK   Minimum Additive Latency
       parameter AL_MAX           =       5; // AL     tCK   Maximum Additive Latency
       parameter CL_MIN           =       3; // CL     tCK   Minimum CAS Latency
       parameter CL_MAX           =       6; // CL     tCK   Maximum CAS Latency
       parameter WR_MIN           =       2; // WR     tCK   Minimum Write Recovery
       parameter WR_MAX           =       6; // WR     tCK   Maximum Write Recovery
       parameter BL_MIN           =       4; // BL     tCK   Minimum Burst Length
       parameter BL_MAX           =       8; // BL     tCK   Minimum Burst Length
       // Clock
       parameter TCK_MAX          =    8000; // tCK    ps    Maximum Clock Cycle Time
       parameter TCH_MIN          =    0.48; // tCH    tCK   Minimum Clock High-Level Pulse Width
       parameter TCH_MAX          =    0.52; // tCH    tCK   Maximum Clock High-Level Pulse Width
       parameter TCL_MIN          =    0.48; // tCL    tCK   Minimum Clock Low-Level Pulse Width
       parameter TCL_MAX          =    0.52; // tCL    tCK   Maximum Clock Low-Level Pulse Width
       // Data
       parameter TLZ              =     TAC; // tLZ    ps    Data-out low-impedance window from CK/CK#