sim.do

Xilinx DDR2存储器接口调试代码

###############################################################################
## Copyright (c) 2007 Xilinx, Inc.
## This design is confidential and proprietary of Xilinx, Inc. 
## All Rights Reserved 
###############################################################################
##   ____  ____
##  /   /\/   /
## /___/  \  /    Vendor             : Xilinx
## \   \   \/     Version            : $Name: i+IP+131489 $
##  \   \         Application        : MIG
##  /   /         Filename           : sim.do
## /___/   /\     Date Last Modified : $Date: 2007/09/21 15:23:17 $
## \   \  /  \    Date Created       : Mon May 14 2007
##  \___\/\___\
##
##Device: Spartan-3/3A/3A-DSP
##Purpose:
##    Sample sim .do file to compile and simulate memory interface
##    design and run the simulation for specified period of time. Display the 
##    waveforms that are listed with "add wave" command. 
##    Assumptions:
##      - Simulation takes place in \sim folder of MIG output directory
##Reference:
##Revision History:
###############################################################################
vlib work
#Map the required libraries here.#
#Complie design parameter file first. This is required for VHDL designs which #
#include a parameter file.#
vlog  ../rtl/*parameters*
#Compile all modules#
vlog  ../rtl/*
#Compile files in sim folder (excluding model parameter file)#
vlog  ../sim/*.v

#Pass the parameters for memory model parameter file#
vlog  +incdir+. +define+x512Mb +define+sg5E +define+x16 ddr2_model.v
#Load the design. Use required libraries.#
vsim -t ps +notimingchecks -L unisims_ver work.sim_tb_top glbl
onerror {resume}
#Log all the objects in design. These will appear in .wlf file#
log -r /*
#View sim_tb_top signals in waveform#
add wave sim:/sim_tb_top/*
#Change radix to Hexadecimal#
radix hex
#Supress Numeric Std package and Arith package warnings.#
#For VHDL designs we get some warnings due to unknown values on some signals at startup#
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0#
#We may also get some Arithmetic package warnings because of unknown values on#
#some of the signals that are used in an Arithmetic operation.#
#In order to suppress these warnings, we use following two commands#
set NumericStdNoWarnings 1
set StdArithNoWarnings 1
#Choose simulation run time by inserting a breakpoint and then run for specified #
#period. Refer simulation_help file.#
when {/sim_tb_top/init_done = 1} {
if {[when -label a_100] == ""} {
when -label a_100 { $now = 50 us } {
nowhen a_100
report simulator control
report simulator state
if {[examine /sim_tb_top/error] == 0} {
echo "TEST PASSED"
quit
}
if {[examine /sim_tb_top/error] != 0} {
echo "TEST FAILED: DATA ERROR"
quit
}
}
}
}

#In case Initialization fails to complete, choose the run time and then quit#
when {$now = @500 us} {
echo "TEST FAILED: INITIALIZATION DID NOT COMPLETE"
quit
}
run -all
quit