log.txt

Xilinx DDR2存储器接口调试代码

                                                          Log file                                                       

Generated by MIG Version MIG 2.0 on Tue Nov 27 17:27:59 2007


Reading design libraries of xc3sd1800a-fg676... successful !
Creating the directory C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design...successful.
...successful!
Creating the directory C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/par...successful!
Creating the directory C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/docs ...successful! 
Creating the directory C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/synth ...successful! 
Creating the directory C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/sim ...successful! 
Creating the directory C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl ...successful! 

/*******************************************************/
/*			     Controller 0		                
/*******************************************************/
Checking pins allocated to Data bits ...
Checking pins allocated to Strobe bits ... 
Checking pins allocated to Mask bits ...
Checking pins allocated to Clock bits ... 
Checking pins allocated to user_interface bits ...
Checking pins allocated to user_interface bits ...
Checking pins allocated to user_interface bits ...
Checking pins allocated to Address bits ...
Checking pins allocated to user_interface bits ...
Checking pins allocated to BankAddress bits ...
Copying all the files from docs ...
copying C:/xilinx92/coregen/ip/xilinx/other/com/xilinx/ip/mig_v2_0/bin/nt/../../data/docs/spartan3/ddr2_sdram/768c.pdf to C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/docs
copying C:/xilinx92/coregen/ip/xilinx/other/com/xilinx/ip/mig_v2_0/bin/nt/../../data/docs/spartan3/ddr2_sdram/xapp454_sp3.url to C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/docs
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_cal_top.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_clk_dcm.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_dqs_delay.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_infrastructure.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_rd_gray_cntr.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_s3_dq_iob.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_tap_dly.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_wr_gray_cntr.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/sim/ddr2_32Mx32_addr_gen_0.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/sim/ddr2_32Mx32_cmd_fsm_0.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_controller_iobs_0.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_s3_dm_iob_0.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_data_path_0.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_fifo_0_wr_en_0.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_fifo_1_wr_en_0.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_infrastructure_top_0.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_parameters_0.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/sim/ddr2_32Mx32_cmp_data_0.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_parameters_0.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_cal_ctl_0.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/sim/ddr2_32Mx32_main_0.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_top_0.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_controller_0.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_data_read_0.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_ram8d_0.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_data_read_controller_0.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_data_write_0.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_iobs_0.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_data_path_iobs_0.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_infrastructure_iobs_0.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_s3_dqs_iob.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/sim/ddr2_32Mx32_test_bench_0.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/sim/ddr2_32Mx32_lfsr32_0.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32_sdc_constraints_0.v ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/sim/sim_tb_top.v ...successful!

Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/par/ddr2_32Mx32.ucf ...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/synth/ddr2_32Mx32.sdc...successful!
Generating the file C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/ddr2_32Mx32.v......successful! 

Allocating pins for the signals.....

Verifying proximity rules for local clock distribution...
Verifying proximity rules for local clock distribution...
Verifying proximity rules for local clock distribution...
Verifying proximity rules for local clock distribution...
Verifying proximity rules for local clock distribution...
Verifying proximity rules for local clock distribution...
Verifying proximity rules for local clock distribution...
	Rule met... generating pinouts for set 0 to 7
Verifying proximity rules for local clock distribution...
	Rule met... generating pinouts for set 8 to 15
Verifying proximity rules for local clock distribution...
	Rule met... generating pinouts for set 16 to 23
Verifying proximity rules for local clock distribution...
	Rule met... generating pinouts for set 24 to 31


Successfully generated "DDR2_SDRAM" interface for controller 0.


*******************************************
Successfully generated DDR2_DQS_N interface.
Look at C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/rtl/
C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/synth/
C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/docs  and
C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/par for output files.
Run the C:/SpeedWay/Fall_07/DDR2/Lab1/ddr2_32Mx32_vlog/ddr2_32Mx32/user_design/par/ise_flow.bat file to create the ncd file.
Pin allocation  ...successful.

Result:
Successful.