set_ise_prop.txt

Xilinx DDR2存储器接口调试代码

NewProject(test.ise)

SetProperty(Device Family, spartan-3a dsp)

SetProperty(Device,xc3sd1800a)

SetProperty(Package,fg676, project)

SetProperty(Speed Grade, -4, project)

SetProperty(Synthesis Tool, XST (VHDL/Verilog), project)

SetProperty(Simulator, ISE Simulator (VHDL/Verilog), project)

AddSource(../rtl/ddr2_32Mx32_parameters_0.v)
AddSource(../rtl/ddr2_32Mx32.v)
AddSource(../rtl/ddr2_32Mx32_cal_ctl_0.v)
AddSource(../rtl/ddr2_32Mx32_cal_top.v)
AddSource(../rtl/ddr2_32Mx32_clk_dcm.v)
AddSource(../rtl/ddr2_32Mx32_controller_0.v)
AddSource(../rtl/ddr2_32Mx32_controller_iobs_0.v)
AddSource(../rtl/ddr2_32Mx32_data_path_0.v)
AddSource(../rtl/ddr2_32Mx32_data_path_iobs_0.v)
AddSource(../rtl/ddr2_32Mx32_data_read_0.v)
AddSource(../rtl/ddr2_32Mx32_data_read_controller_0.v)
AddSource(../rtl/ddr2_32Mx32_data_write_0.v)
AddSource(../rtl/ddr2_32Mx32_dqs_delay.v)
AddSource(../rtl/ddr2_32Mx32_fifo_0_wr_en_0.v)
AddSource(../rtl/ddr2_32Mx32_fifo_1_wr_en_0.v)
AddSource(../rtl/ddr2_32Mx32_infrastructure.v)
AddSource(../rtl/ddr2_32Mx32_infrastructure_iobs_0.v)
AddSource(../rtl/ddr2_32Mx32_infrastructure_top_0.v)
AddSource(../rtl/ddr2_32Mx32_iobs_0.v)
AddSource(../rtl/ddr2_32Mx32_ram8d_0.v)
AddSource(../rtl/ddr2_32Mx32_rd_gray_cntr.v)
AddSource(../rtl/ddr2_32Mx32_s3_dm_iob_0.v)
AddSource(../rtl/ddr2_32Mx32_s3_dq_iob.v)
AddSource(../rtl/ddr2_32Mx32_s3_dqs_iob.v)
AddSource(../rtl/ddr2_32Mx32_tap_dly.v)
AddSource(../rtl/ddr2_32Mx32_top_0.v)
AddSource(../rtl/ddr2_32Mx32_wr_gray_cntr.v)

AddSource(ddr2_32Mx32.ucf,ddr2_32Mx32)

SetProperty(Optimization Goal,Speed,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Optimization Effort,High,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Synthesis Constraints File,../synth/mem_interface_top.xcf,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Library Search Order,../synth/ddr2_32Mx32.lso,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Keep Hierarchy,Soft,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Generate RTL Schematic,Yes,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Read Cores,True,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Write Timing Constraints,True,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Cross Clock Analysis,False,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Hierarchy Separator,/,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Bus Delimiter,(),ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Case,Maintain,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Slice Utilization Ratio,100,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Verilog 2001,True,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(FSM Encoding Algorithm,Auto,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(FSM Style,LUT,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(RAM Extraction,True,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(RAM Style,Auto,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(ROM Extraction,True,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(ROM Style,Auto,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Mux Extraction,Yes,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Mux Style,Auto,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Decoder Extraction,True,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Priority Encoder Extraction,Yes,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Shift Register Extraction,True,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Logical Shifter Extraction,True,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(XOR Collapsing,True,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Resource Sharing,True,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Add I/O Buffers,True,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Max Fanout,500,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Number of Clock Buffers,8,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Register Duplication,False,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Equivalent Register Removal,False,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Register Balancing,No,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Slice Packing,True,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Optimize Instantiated Primitives,False,ddr2_32Mx32,Synthesize - XST, 4)
SetProperty(Pack I/O Registers into IOBs,No,ddr2_32Mx32,Synthesize - XST, 4)

SetProperty(Allow Unexpanded Blocks,True,ddr2_32Mx32,Translate, 4)

SetProperty(Optimization Strategy (Cover Mode),Speed,ddr2_32Mx32,Map, 4)
SetProperty(Pack I/O Registers/Latches into IOBs,For Inputs and Outputs,ddr2_32Mx32,Map, 4)
SetProperty(Map to Input Functions,8,ddr2_32Mx32,Map, 4)

SetProperty(Place & Route Effort Level (Overall),Medium,ddr2_32Mx32,Place & Route, 4)
SetProperty(Starting Placer Cost Table (1-100),1,ddr2_32Mx32,Place & Route, 4)
SetProperty(Generate Post-Place & Route Static Timing Report,True,ddr2_32Mx32,Place & Route, 4)

SetProperty(Number of Items in Error/Verbose Report (0 - 2 Billion),100,ddr2_32Mx32,Generate Post-Map Static Timing, 4)

SetProperty(Enable Debugging of Serial Mode BitStream,False,ddr2_32Mx32,Generate Programming File, 4)
SetProperty(Create Binary Configuration File,False,ddr2_32Mx32,Generate Programming File, 4)
SetProperty(Enable Cyclic Redundancy Checking (CRC),True,ddr2_32Mx32,Generate Programming File, 4)
SetProperty(Configuration Rate,6,ddr2_32Mx32,Generate Programming File, 4)
SetProperty(Configuration Pin Program,Pull Up,ddr2_32Mx32,Generate Programming File, 4)
SetProperty(Configuration Pin Done,Pull Up,ddr2_32Mx32,Generate Programming File, 4)
SetProperty(JTAG Pin TCK,Pull Up,ddr2_32Mx32,Generate Programming File, 4)
SetProperty(JTAG Pin TDI,Pull Up,ddr2_32Mx32,Generate Programming File, 4)
SetProperty(JTAG Pin TDO,Pull Up,ddr2_32Mx32,Generate Programming File, 4)
SetProperty(JTAG Pin TMS,Pull Up,ddr2_32Mx32,Generate Programming File, 4)
SetProperty(Unused IOB Pins,Float,ddr2_32Mx32,Generate Programming File, 4)
SetProperty(UserID Code (8 Digit Hexadecimal),0xFFFFFFFF,ddr2_32Mx32,Generate Programming File, 4)
SetProperty(FPGA Start-Up Clock,JTAG Clock,ddr2_32Mx32,Generate Programming File, 4)
SetProperty(Done (Output Events),Default (4),ddr2_32Mx32,Generate Programming File, 4)
SetProperty(Enable Outputs (Output Events),Default (5),ddr2_32Mx32,Generate Programming File, 4)
SetProperty(Release Write Enable (Output Events),Default (6),ddr2_32Mx32,Generate Programming File, 4)
SetProperty(Release DLL (Output Events),Default (NoWait),ddr2_32Mx32,Generate Programming File, 4)
SetProperty(Enable Internal Done Pipe,False,ddr2_32Mx32,Generate Programming File, 4)
SetProperty(Drive Done Pin High,False,ddr2_32Mx32,Generate Programming File, 4)
SetProperty(Security,Enable Readback and Reconfiguration,ddr2_32Mx32,Generate Programming File, 4)

CloseProject(test.ise)