ddr2_32mx32.ucf

Xilinx DDR2存储器接口调试代码

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[10].r" RLOC=X0Y5;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[10].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[11].r" RLOC=X0Y5;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[11].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[12].r" RLOC=X1Y4;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[12].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[13].r" RLOC=X1Y4;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[13].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[14].r" RLOC=X1Y5;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[14].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[15].r" RLOC=X1Y5;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[15].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[16].r" RLOC=X0Y2;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[16].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[17].r" RLOC=X0Y2;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[17].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[18].r" RLOC=X0Y3;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[18].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[19].r" RLOC=X0Y3;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[19].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[20].r" RLOC=X1Y2;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[20].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[21].r" RLOC=X1Y2;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[21].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[22].r" RLOC=X1Y3;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[22].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[23].r" RLOC=X1Y3;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[23].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[24].r" RLOC=X0Y0;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[24].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[25].r" RLOC=X0Y0;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[25].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[26].r" RLOC=X0Y1;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[26].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[27].r" RLOC=X0Y1;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[27].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[28].r" RLOC=X1Y0;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[28].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[29].r" RLOC=X1Y0;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[29].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[30].r" RLOC=X1Y1;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[30].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[31].r" RLOC=X1Y1;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[31].r" U_SET = delay_calibration_chain;

#####################################################################################################################
## BEL constraints for LUTS in tap delay ckt
#####################################################################################################################
INST "infrastructure_top0/cal_top0/tap_dly0/l0"  BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l1"  BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l2"  BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l3"  BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l4"  BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l5"  BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l6"  BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l7"  BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l8"  BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l9"  BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l10" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l11" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l12" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l13" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l14" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l15" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l16" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l17" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l18" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l19" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l20" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l21" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l22" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l23" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l24" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l25" BEL= F;  
INST "infrastructure_top0/cal_top0/tap_dly0/l26" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l27" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l28" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l29" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l30" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l31" BEL= F;

##############################################################################################################
## MAXDELAY constraints
##############################################################################################################

##############################################################################################################
## Constraint to have the tap delay inverter connection wire length to be the same and minimum to get
## accurate calibration of tap delays. The following constraints are independent of frequency. This delay 
## varies from device to device. The reported delay will be in the range of 300 to 600 ps
##############################################################################################################
NET "infrastructure_top0/cal_top0/tap_dly0/tap[7]"  MAXDELAY = 600ps;
NET "infrastructure_top0/cal_top0/tap_dly0/tap[15]" MAXDELAY = 600ps;
NET "infrastructure_top0/cal_top0/tap_dly0/tap[23]" MAXDELAY = 600ps;

##############################################################################################################
## Constraint from the dqs PAD to input of LUT delay element. The reported delay will be in the range of 
## 400 to 860 ps.
##############################################################################################################
NET "top_00/dqs_int_delay_in*" MAXDELAY = 860ps;

##############################################################################################################
## Constraint from rst_dqs_div_in PAD to input of LUT delay element. The reported delay will be in the range 
## of 400 to 860ps.
##############################################################################################################
NET "top_00/dqs_div_rst" MAXDELAY = 860ps;



##############################################################################################################
## RLOC Origin constraint for LUT delay calibration chain.
##############################################################################################################
INST "infrastructure_top0/cal_top0/tap_dly0/l0" RLOC_ORIGIN = X42Y154;

##############################################################################################################
## Area Group Constraint For tap_dly and cal_ctl module.
##############################################################################################################
INST "infrastructure_top0/cal_top0/cal_ctl0" AREA_GROUP = cal_ctl;
INST "infrastructure_top0/cal_top0/tap_dly0" AREA_GROUP = cal_ctl;
AREA_GROUP "cal_ctl" RANGE = SLICE_X42Y154:SLICE_X53Y167;
AREA_GROUP "cal_ctl" GROUP = CLOSED;

##############################################################################################################

#***********************************************************************************************************#
#                        CONTROLLER 0 
#***********************************************************************************************************#

##############################################################################################################
## I/O STANDARDS
##############################################################################################################
NET  "cntrl0_ddr2_dq[*]"                        IOSTANDARD = SSTL18_II;
NET  "cntrl0_ddr2_a[*]"                         IOSTANDARD = SSTL18_I;
NET  "cntrl0_ddr2_ba[*]"                        IOSTANDARD = SSTL18_I;
NET  "cntrl0_ddr2_cke"                          IOSTANDARD = SSTL18_I;
NET  "cntrl0_ddr2_cs_n"                         IOSTANDARD = SSTL18_I;
NET  "cntrl0_ddr2_ras_n"                        IOSTANDARD = SSTL18_I;
NET  "cntrl0_ddr2_cas_n"                        IOSTANDARD = SSTL18_I;
NET  "cntrl0_ddr2_we_n"                         IOSTANDARD = SSTL18_I;
NET  "cntrl0_ddr2_odt"                          IOSTANDARD = SSTL18_I;
NET  "cntrl0_ddr2_dm[*]"                        IOSTANDARD = SSTL18_II;
NET  "cntrl0_rst_dqs_div_in"                    IOSTANDARD = SSTL18_II;
NET  "cntrl0_rst_dqs_div_out"                   IOSTANDARD = SSTL18_II;
NET  "sys_clkb"                                 IOSTANDARD = LVDS_25;
NET  "sys_clk"                                  IOSTANDARD = LVDS_25;
NET  "reset_in_n"                               IOSTANDARD = LVCMOS18;
NET  "cntrl0_ddr2_dqs[*]"                       IOSTANDARD = DIFF_SSTL18_II;
NET  "cntrl0_ddr2_dqs_n[*]"                     IOSTANDARD = DIFF_SSTL18_II;
NET  "cntrl0_ddr2_ck[*]"                        IOSTANDARD = DIFF_SSTL18_II;
NET  "cntrl0_ddr2_ck_n[*]"                      IOSTANDARD = DIFF_SSTL18_II;


##############################################################################################################
# Banks 0
# Pin Location Constraints for System clock signals
##############################################################################################################
NET  "sys_clkb"                                   LOC = "C13";
NET  "sys_clk"                                    LOC = "B13";

##############################################################################################################
# Banks 3
# Pin Location Constraints for Clock,Masks, Address, and Controls