ddr2_32mx32.ucf

Xilinx DDR2存储器接口调试代码

##############################################################################################################
##
##  Xilinx, Inc. 2007            www.xilinx.com  
##  Tue November 27 17:27: 2007
##
##  
##############################################################################################################
##  File name :       ddr2_32Mx32.ucf
## 
##  Description :     Constraints file
##                    targetted to FPGA: xc3sd1800afg676
##                    Speed Grade:       -4
##                    FPGA family:       spartan3adsp
##                    Design Entry:      verilog
##                    Frequency:         125 MHz
##                    Data width:        32
##                    Memory:            DDR2_SDRAM/Components/MT47H32M16XX-5E
##                    Design:            without Test bench
##                    DCM Used:          Enabled
##
##############################################################################################################

##############################################################################################################
## Clock constraints
##############################################################################################################
NET "infrastructure_top0/sys_clk_ibuf" TNM_NET = "SYS_CLK";
TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK"  8.000000  ns HIGH 50 %;
##############################################################################################################

##############################################################################################################
## This paths are constrained to get rid of unconstrained paths.
##############################################################################################################
NET "infrastructure_top0/clk_dcm0/clk" TNM_NET = "clk0";
NET "top_00/data_path0/dqs_delayed_col*" TNM_NET = "dqs_clk";
TIMESPEC "TS_CLK" = FROM "clk0" TO "dqs_clk"  18 ns DATAPATHONLY;

NET "infrastructure_top0/clk_dcm0/clk90" TNM_NET = "clk90";
TIMESPEC "TS_CLK90" = FROM "dqs_clk" TO "clk90" 18 ns DATAPATHONLY;

NET "top_00/data_path0/data_read0/gen_strobe*strobe/wclk*" TNM_NET = "fifo_clk";
TIMESPEC "TS_DQS_CLK" = FROM "dqs_clk" TO "fifo_clk"  5 ns DATAPATHONLY;

NET "top_00/data_path0/data_read_controller0/gen_wr_en*fifo*_wr_en_inst/clk" TNM_NET = "fifo_we_clk";
TIMESPEC "TS_WE_CLK" = FROM "dqs_clk" TO "fifo_we_clk"  5 ns DATAPATHONLY;

NET "top_00/data_path0/data_read_controller0/gen_wr_addr*fifo*_wr_addr_inst/clk" TNM_NET = "fifo_waddr_clk";
TIMESPEC "TS_WADDR_CLK" = FROM "dqs_clk" TO "fifo_waddr_clk"  5 ns DATAPATHONLY;

#############################################################################################################
## Calibration Circuit Constraints
#############################################################################################################
## Placement constraints for LUTS in tap delay ckt
#############################################################################################################
INST "infrastructure_top0/cal_top0/tap_dly0/l0" RLOC=X0Y6;
INST "infrastructure_top0/cal_top0/tap_dly0/l0" U_SET = delay_calibration_chain;
 
INST "infrastructure_top0/cal_top0/tap_dly0/l1" RLOC=X0Y6;
INST "infrastructure_top0/cal_top0/tap_dly0/l1" U_SET = delay_calibration_chain;
 
INST "infrastructure_top0/cal_top0/tap_dly0/l2" RLOC=X0Y7;
INST "infrastructure_top0/cal_top0/tap_dly0/l2" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/l3" RLOC=X0Y7;
INST "infrastructure_top0/cal_top0/tap_dly0/l3" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/l4" RLOC=X1Y6;
INST "infrastructure_top0/cal_top0/tap_dly0/l4" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/l5" RLOC=X1Y6;
INST "infrastructure_top0/cal_top0/tap_dly0/l5" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/l6" RLOC=X1Y7;
INST "infrastructure_top0/cal_top0/tap_dly0/l6" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/l7" RLOC=X1Y7;
INST "infrastructure_top0/cal_top0/tap_dly0/l7" U_SET = delay_calibration_chain;
  
INST "infrastructure_top0/cal_top0/tap_dly0/l8" RLOC=X0Y4;
INST "infrastructure_top0/cal_top0/tap_dly0/l8" U_SET = delay_calibration_chain;
 
INST "infrastructure_top0/cal_top0/tap_dly0/l9" RLOC=X0Y4;
INST "infrastructure_top0/cal_top0/tap_dly0/l9" U_SET = delay_calibration_chain;
 
INST "infrastructure_top0/cal_top0/tap_dly0/l10" RLOC=X0Y5;
INST "infrastructure_top0/cal_top0/tap_dly0/l10" U_SET = delay_calibration_chain;
 
INST "infrastructure_top0/cal_top0/tap_dly0/l11" RLOC=X0Y5;
INST "infrastructure_top0/cal_top0/tap_dly0/l11" U_SET = delay_calibration_chain;
 
INST "infrastructure_top0/cal_top0/tap_dly0/l12" RLOC=X1Y4;
INST "infrastructure_top0/cal_top0/tap_dly0/l12" U_SET = delay_calibration_chain;
 
INST "infrastructure_top0/cal_top0/tap_dly0/l13" RLOC=X1Y4;
INST "infrastructure_top0/cal_top0/tap_dly0/l13" U_SET = delay_calibration_chain;
 
INST "infrastructure_top0/cal_top0/tap_dly0/l14" RLOC=X1Y5;
INST "infrastructure_top0/cal_top0/tap_dly0/l14" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/l15" RLOC=X1Y5;
INST "infrastructure_top0/cal_top0/tap_dly0/l15" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/l16" RLOC=X0Y2;
INST "infrastructure_top0/cal_top0/tap_dly0/l16" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/l17" RLOC=X0Y2;
INST "infrastructure_top0/cal_top0/tap_dly0/l17" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/l18" RLOC=X0Y3;
INST "infrastructure_top0/cal_top0/tap_dly0/l18" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/l19" RLOC=X0Y3;
INST "infrastructure_top0/cal_top0/tap_dly0/l19" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/l20" RLOC=X1Y2;
INST "infrastructure_top0/cal_top0/tap_dly0/l20" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/l21" RLOC=X1Y2;
INST "infrastructure_top0/cal_top0/tap_dly0/l21" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/l22" RLOC=X1Y3;
INST "infrastructure_top0/cal_top0/tap_dly0/l22" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/l23" RLOC=X1Y3;
INST "infrastructure_top0/cal_top0/tap_dly0/l23" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/l24" RLOC=X0Y0;
INST "infrastructure_top0/cal_top0/tap_dly0/l24" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/l25" RLOC=X0Y0;
INST "infrastructure_top0/cal_top0/tap_dly0/l25" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/l26" RLOC=X0Y1;
INST "infrastructure_top0/cal_top0/tap_dly0/l26" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/l27" RLOC=X0Y1;
INST "infrastructure_top0/cal_top0/tap_dly0/l27" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/l28" RLOC=X1Y0;
INST "infrastructure_top0/cal_top0/tap_dly0/l28" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/l29" RLOC=X1Y0;
INST "infrastructure_top0/cal_top0/tap_dly0/l29" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/l30" RLOC=X1Y1;
INST "infrastructure_top0/cal_top0/tap_dly0/l30" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/l31" RLOC=X1Y1;
INST "infrastructure_top0/cal_top0/tap_dly0/l31" U_SET = delay_calibration_chain;

#################################################################################################################
# Placement constraints for first stage flops in tap delay ckt
#################################################################################################################
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[0].r" RLOC=X0Y6;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[0].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[1].r" RLOC=X0Y6;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[1].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[2].r" RLOC=X0Y7;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[2].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[3].r" RLOC=X0Y7;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[3].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[4].r" RLOC=X1Y6;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[4].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[5].r" RLOC=X1Y6;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[5].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[6].r" RLOC=X1Y7;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[6].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[7].r" RLOC=X1Y7;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[7].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[8].r" RLOC=X0Y4;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[8].r" U_SET = delay_calibration_chain;

INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[9].r" RLOC=X0Y4;
INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[9].r" U_SET = delay_calibration_chain;