ddr2_32mx32.prj

Xilinx DDR2存储器接口调试代码

verilog  work  ../rtl/ddr2_32Mx32.v
verilog  work  ../rtl/ddr2_32Mx32_cal_ctl_0.v
verilog  work  ../rtl/ddr2_32Mx32_cal_top.v
verilog  work  ../rtl/ddr2_32Mx32_clk_dcm.v
verilog  work  ../rtl/ddr2_32Mx32_controller_0.v
verilog  work  ../rtl/ddr2_32Mx32_controller_iobs_0.v
verilog  work  ../rtl/ddr2_32Mx32_data_path_0.v
verilog  work  ../rtl/ddr2_32Mx32_data_path_iobs_0.v
verilog  work  ../rtl/ddr2_32Mx32_data_read_0.v
verilog  work  ../rtl/ddr2_32Mx32_data_read_controller_0.v
verilog  work  ../rtl/ddr2_32Mx32_data_write_0.v
verilog  work  ../rtl/ddr2_32Mx32_dqs_delay.v
verilog  work  ../rtl/ddr2_32Mx32_fifo_0_wr_en_0.v
verilog  work  ../rtl/ddr2_32Mx32_fifo_1_wr_en_0.v
verilog  work  ../rtl/ddr2_32Mx32_infrastructure.v
verilog  work  ../rtl/ddr2_32Mx32_infrastructure_iobs_0.v
verilog  work  ../rtl/ddr2_32Mx32_infrastructure_top_0.v
verilog  work  ../rtl/ddr2_32Mx32_iobs_0.v
verilog  work  ../rtl/ddr2_32Mx32_parameters_0.v
verilog  work  ../rtl/ddr2_32Mx32_ram8d_0.v
verilog  work  ../rtl/ddr2_32Mx32_rd_gray_cntr.v
verilog  work  ../rtl/ddr2_32Mx32_s3_dm_iob_0.v
verilog  work  ../rtl/ddr2_32Mx32_s3_dq_iob.v
verilog  work  ../rtl/ddr2_32Mx32_s3_dqs_iob.v
verilog  work  ../rtl/ddr2_32Mx32_tap_dly.v
verilog  work  ../rtl/ddr2_32Mx32_top_0.v
verilog  work  ../rtl/ddr2_32Mx32_wr_gray_cntr.v