mig.prj

Xilinx DDR2存储器接口调试代码

<?xml version="1.0" encoding="UTF-8"?>
<Project NoOfControllers="1" >
    <DCM>1</DCM>
    <ModuleName>ddr2_32Mx32</ModuleName>
    <Class>Class I</Class>
    <FPGADevice/>
    <Controller number="0" >
        <MemoryDevice>DDR2_SDRAM/Components/MT47H32M16XX-5E</MemoryDevice>
        <Clocking>Local clocking</Clocking>
        <Frequency>125</Frequency>
        <DataWidth>32</DataWidth>
        <RowAddress>13</RowAddress>
        <ColAddress>10</ColAddress>
        <BankAddress>2</BankAddress>
        <TimingParameters>
            <Parameters twtr="10" tjit="100" tdh="400" tis="600" tdqsq="350" tqhs="450" twr="15" trtp="7.5" trfc="105" trp="15" tds="400" tmrd="2" tih="600" tac="600" tras="40" trc="55" trcd="15" />
        </TimingParameters>
        <WritePipeLine>4</WritePipeLine>
        <BankSelection>
            <Bank Control="0" SysClk="1" Data="0" name="0" Address="0" wasso="76" />
            <Bank Control="1" SysClk="0" Data="1" name="3" Address="1" wasso="105" />
        </BankSelection>
        <mrBurstLength name="Burst Length" >8(011)</mrBurstLength>
        <mrBurstType name="Burst Type" >sequential(0)</mrBurstType>
        <mrCasLatency name="CAS Latency" >3(011)</mrCasLatency>
        <mrMode name="Mode" >normal(0)</mrMode>
        <mrDllReset name="DLL Reset" >yes(1)</mrDllReset>
        <mrPdMode name="PD Mode" >fast exit(0)</mrPdMode>
        <mrWriteRecovery name="Write Recovery" >3(010)</mrWriteRecovery>
        <emrDllEnable name="DLL Enable" >Enable-Normal(0)</emrDllEnable>
        <emrOutputDriveStrength name="Output Drive Strength" >Fullstrength(0)</emrOutputDriveStrength>
        <emrRTT name="RTT (nominal) - ODT" >50ohms(11)</emrRTT>
        <emrPosted name="Additive Latency (AL)" >0(000)</emrPosted>
        <emrOCD name="OCD Operation" >OCD Exit(000)</emrOCD>
        <emrDQS name="DQS# Enable" >Enable(0)</emrDQS>
        <emrRDQS name="RDQS Enable" >Disable(0)</emrRDQS>
        <emrOutputs name="Outputs" >Enable(0)</emrOutputs>
    </Controller>
</Project>