ddr2_32mx32_clk_dcm.v

Xilinx DDR2存储器接口调试代码

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005-2007 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor			: Xilinx
// \   \   \/    Version		: $Name: i+IP+131489 $
//  \   \        Application		: MIG
//  /   /        Filename		: ddr2_32Mx32_clk_dcm.v
// /___/   /\    Date Last Modified	: $Date: 2007/09/21 15:23:17 $
// \   \  /  \   Date Created		: Mon May 2 2005
//  \___\/\___\
// Device	: Spartan-3/3A/3A-DSP
// Design Name	: DDR2 SDRAM
// Purpose	: This module has the DCM instantiation to DDR2 SDRAM controller
////////////////////////////////////////////////////////////////////////////////

`timescale 1ns/100ps
module ddr2_32Mx32_clk_dcm
  (
   input  input_clk,
   input  rst,
   output clk,
   output clk90,
   output dcm_lock
   );

   localparam GND = 1'b0;

   wire   clk0dcm;
   wire   clk90dcm;
   wire   clk0_buf;
   wire   clk90_buf;
   wire   dcm1_lock;
   
   assign clk      = clk0_buf;
   assign clk90	   = clk90_buf;
   assign dcm_lock = dcm1_lock;

   DCM # 
     (
      .DLL_FREQUENCY_MODE    ("LOW"),
      .DUTY_CYCLE_CORRECTION ("TRUE")
      )
     DCM_INST1
     (
      .CLKIN    (input_clk),
      .CLKFB    (clk0_buf),
      .DSSEN    (GND),
      .PSINCDEC (GND),
      .PSEN     (GND),
      .PSCLK    (GND),
      .RST      (rst),
      .CLK0     (clk0dcm),
      .CLK90    (clk90dcm),
      .CLK180   (),
      .CLK270   (),
      .CLK2X    (),
      .CLK2X180 (),
      .CLKDV    (),
      .CLKFX    (),
      .CLKFX180 (),
      .LOCKED   (dcm1_lock),
      .PSDONE   (),
      .STATUS   ()
      );


   BUFGMUX BUFG_CLK0
     (
      .O  (clk0_buf),
      .I0 (clk0dcm),
      .I1 (clk0dcm),
      .S  (1'b0)
      );
   BUFGMUX BUFG_CLK90
     (
      .O  (clk90_buf),
      .I0 (clk90dcm),
      .I1 (clk90dcm),
      .S  (1'b0)
      );
   
endmodule