ddr2_32mx32.v

Xilinx DDR2存储器接口调试代码

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005-2007 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor			: Xilinx
// \   \   \/    Version		: $Name: i+IP+131489 $
//  \   \        Application		: MIG
//  /   /        Filename		: ddr2_32Mx32.v
// /___/   /\    Date Last Modified	: $Date: 2007/09/21 15:23:18 $
// \   \  /  \   Date Created		: Mon May 2 2005
//  \___\/\___\
// Device	: Spartan-3/3A/3A-DSP
// Design Name	: DDR2 SDRAM
// Purpose	: This module has the instantiations main and infrastructure_top
//		  modules
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns/100ps
module ddr2_32Mx32
  (
   inout [31:0] cntrl0_ddr2_dq,
   output [12:0] cntrl0_ddr2_a,
   output [1:0] cntrl0_ddr2_ba,
   output  cntrl0_ddr2_cke,
   output  cntrl0_ddr2_cs_n,
   output  cntrl0_ddr2_ras_n,
   output  cntrl0_ddr2_cas_n,
   output  cntrl0_ddr2_we_n,
   output  cntrl0_ddr2_odt,
   output [3:0] cntrl0_ddr2_dm,
   input  cntrl0_rst_dqs_div_in,
   output  cntrl0_rst_dqs_div_out,
   input  sys_clkb,
   input  sys_clk,
   input  reset_in_n,
   input  cntrl0_burst_done,
   output  cntrl0_init_done,
   output  cntrl0_ar_done,
   output  cntrl0_user_data_valid,
   output  cntrl0_auto_ref_req,
   output  cntrl0_user_cmd_ack,
   input [2:0] cntrl0_user_command_register,
   output  cntrl0_clk_tb,
   output  cntrl0_clk90_tb,
   output  cntrl0_sys_rst_tb,
   output  cntrl0_sys_rst90_tb,
   output  cntrl0_sys_rst180_tb,
   input [7:0] cntrl0_user_data_mask,
   output [63:0] cntrl0_user_output_data,
   input [63:0] cntrl0_user_input_data,
   input [25:0] cntrl0_user_input_address,
   inout [3:0] cntrl0_ddr2_dqs,
   inout [3:0] cntrl0_ddr2_dqs_n,
   output [1:0] cntrl0_ddr2_ck,
   output [1:0] cntrl0_ddr2_ck_n
   );

   wire       wait_200us;
   wire       clk_0;
   wire       clk90_0;
   wire       sys_rst;
   wire       sys_rst90;
   wire       sys_rst180;
   wire [4:0] delay_sel_val;

ddr2_32Mx32_top_0     top_00
   (
   .ddr2_dq	(cntrl0_ddr2_dq),
   .ddr2_a	(cntrl0_ddr2_a),
   .ddr2_ba	(cntrl0_ddr2_ba),
   .ddr2_cke	(cntrl0_ddr2_cke),
   .ddr2_cs_n	(cntrl0_ddr2_cs_n),
   .ddr2_ras_n	(cntrl0_ddr2_ras_n),
   .ddr2_cas_n	(cntrl0_ddr2_cas_n),
   .ddr2_we_n	(cntrl0_ddr2_we_n),
   .ddr2_odt	(cntrl0_ddr2_odt),
   .ddr2_dm	(cntrl0_ddr2_dm),
   .rst_dqs_div_in	(cntrl0_rst_dqs_div_in),
   .rst_dqs_div_out	(cntrl0_rst_dqs_div_out),
   .burst_done	(cntrl0_burst_done),
   .init_done	(cntrl0_init_done),
   .ar_done	(cntrl0_ar_done),
   .user_data_valid	(cntrl0_user_data_valid),
   .auto_ref_req	(cntrl0_auto_ref_req),
   .user_cmd_ack	(cntrl0_user_cmd_ack),
   .user_command_register	(cntrl0_user_command_register),
   .clk_tb	(cntrl0_clk_tb),
   .clk90_tb	(cntrl0_clk90_tb),
   .sys_rst_tb	(cntrl0_sys_rst_tb),
   .sys_rst90_tb	(cntrl0_sys_rst90_tb),
   .sys_rst180_tb	(cntrl0_sys_rst180_tb),
   .user_data_mask	(cntrl0_user_data_mask),
   .user_output_data	(cntrl0_user_output_data),
   .user_input_data	(cntrl0_user_input_data),
   .user_input_address	(cntrl0_user_input_address),
   .ddr2_dqs	(cntrl0_ddr2_dqs),
   .ddr2_dqs_n	(cntrl0_ddr2_dqs_n),
   .ddr2_ck	(cntrl0_ddr2_ck),
   .ddr2_ck_n	(cntrl0_ddr2_ck_n),
   .wait_200us     (wait_200us),
   .clk_int        (clk_0),
   .clk90_int      (clk90_0),
   .sys_rst        (sys_rst),
   .sys_rst90      (sys_rst90),
   .sys_rst180     (sys_rst180),
   .delay_sel_val  (delay_sel_val)
   );


ddr2_32Mx32_infrastructure_top infrastructure_top0
   (
    .sys_clkb	(sys_clkb),
    .sys_clk	(sys_clk),
    .reset_in_n	(reset_in_n),
    .wait_200us_rout    (wait_200us),
    .delay_sel_val1_val (delay_sel_val),
    .sys_rst_val        (sys_rst),
    .sys_rst90_val      (sys_rst90),
    .clk_int_val        (clk_0),
    .clk90_int_val      (clk90_0),
    .sys_rst180_val     (sys_rst180)
    );

endmodule