ddr2_32mx32_controller_0.v

Xilinx DDR2存储器接口调试代码

                   4'b0001 : begin
                      if (count6 == 6'd1)
                        init_next_state = INIT_LOAD_MODE_REG;
                      else
                        init_next_state = INIT_IDLE;
                   end
                   4'b0010 : begin
                      if (count6 == 6'd1)
                        init_next_state = INIT_LOAD_MODE_REG;
                      else
                        init_next_state = INIT_IDLE;
                   end
                   4'b0011 : begin
                      if (count6 == 6'd1)
                        init_next_state = INIT_LOAD_MODE_REG;
                      else
                        init_next_state = INIT_IDLE;
                   end
                   4'b0100 : begin
                      if (count6 == 6'd1)
                        init_next_state = INIT_LOAD_MODE_REG;                      
                      else
                        init_next_state = INIT_IDLE;
                   end
                   4'b0101 : begin
                      if (count6 == 6'd1)
                        init_next_state = INIT_PRECHARGE;
                      else
                        init_next_state = INIT_IDLE;
                   end
                   4'b0110 : begin
                      if (count6 == 6'd1)
                        init_next_state = INIT_AUTO_REFRESH;
                      else
                        init_next_state = INIT_IDLE;
                   end
                   4'b0111: begin
                      if (count6 == 6'd1)
                        init_next_state = INIT_AUTO_REFRESH;
                      else
                        init_next_state = INIT_IDLE;
                   end
                   4'b1000: begin
                      if (count6 == 6'd1)
                        init_next_state = INIT_LOAD_MODE_REG;
                      else
                        init_next_state = INIT_IDLE;
                   end
                   4'b1001: begin
                      if (count6 == 6'd1)
                        init_next_state = INIT_LOAD_MODE_REG;
                      else
                        init_next_state = init_current_state;
                   end
                   4'b1010: begin
                      if (count6 == 6'd1)
                        init_next_state = INIT_LOAD_MODE_REG;
                      else
                        init_next_state = init_current_state;
                   end
                   4'b1011: begin
                      if (count6 == 6'd1)
                        init_next_state = INIT_IDLE;
                      else
                        init_next_state = init_current_state;
                   end
                   default :
                     init_next_state = INIT_IDLE;
                 endcase
              end
              else
                init_next_state = IDLE;
           end
           INIT_PRECHARGE :
             init_next_state = INIT_IDLE;
           
           INIT_LOAD_MODE_REG :
             init_next_state = INIT_IDLE;
           
           INIT_AUTO_REFRESH :
             init_next_state = INIT_IDLE;
           
           default :
             init_next_state = INIT_IDLE;
         endcase
      end
   end

//******************************************************************************
// Main state machine
//******************************************************************************

   always @ (negedge clk) begin
      if (rst180_r == 1'b1) 
        current_state    <= IDLE;
      else 
        current_state    <= next_state;
   end


   always @ (*) begin
      if (rst180_r == 1'b1)
        next_state = IDLE;
      else begin
         case (current_state)
           IDLE : begin
              if(~init_mem) begin
                 if ( auto_ref == 1'b1  && rfc_count_reg == 1'b1 
                      && rpcnt0 == 1'b1 )
                   next_state = AUTO_REFRESH;
                 else if (go_to_active == 1'b1)
                   next_state = ACTIVE;
                 else
                   next_state = IDLE;
              end
              else
                next_state = IDLE;
           end
           
           PRECHARGE :
             next_state = IDLE;
           
           AUTO_REFRESH :
             next_state = IDLE;
           
           ACTIVE :
             next_state = ACTIVE_WAIT;
           
           ACTIVE_WAIT : begin
              if(rcdw_count == 3'b000  && write_cmd1)
                next_state = FIRST_WRITE;
              else if (rcdr_count == 3'b000 && read_cmd3)
                next_state = BURST_READ;
              else
                next_state = ACTIVE_WAIT;
           end
           
           FIRST_WRITE : begin
              next_state = WRITE_WAIT;
           end
           
           WRITE_WAIT : begin
              case(wrburst_end)
                1'b1 :
                  next_state = PRECHARGE_AFTER_WRITE;
                1'b0 : begin
                   if (wrburst_end_cnt == 3'b010)
                     next_state = BURST_WRITE;
                   else
                     next_state = WRITE_WAIT;
                end
                default :
                  next_state = WRITE_WAIT;
              endcase
           end
           BURST_WRITE : begin
              next_state = WRITE_WAIT;
           end
           PRECHARGE_AFTER_WRITE : begin
              next_state = PRECHARGE_AFTER_WRITE_2;
           end
           PRECHARGE_AFTER_WRITE_2 : begin
              if(wr_count == 3'd0)
                next_state = PRECHARGE;
              else
                next_state = PRECHARGE_AFTER_WRITE_2;
           end
           READ_WAIT : begin
              case(rdburst_end)
                1'b1 :
                  next_state = PRECHARGE_AFTER_WRITE;
                1'b0 : begin
                   if (cas_count == 3'b001)
                     next_state = BURST_READ;
                   else
                     next_state = READ_WAIT;
                end
                default :
                  next_state = READ_WAIT;
              endcase
           end
           BURST_READ : begin
              next_state = READ_WAIT;
           end
           default :
             next_state = IDLE;
         endcase
      end
   end

//******************************************************************************
// Address generation logic
//******************************************************************************
   always @( negedge clk ) begin
      if(rst180_r)
        ddr_address1 <= {`ROW_ADDRESS{1'b0}};
      else if(init_mem)
        case ( init_count )
          4'b0000, 4'b0101 : ddr_address1 <= {`ROW_ADDRESS{1'b0}} |
                                             12'h400;
          4'b0001 : ddr_address1 <= {`ROW_ADDRESS{1'b0}}; 
          4'b0010 : ddr_address1 <= {`ROW_ADDRESS{1'b0}}; 
          4'b0011 : ddr_address1 <= emr; 
          4'b0100 : ddr_address1 <= lmr_dll_rst;
          4'b1000 : ddr_address1 <= lmr_dll_set; 
          4'b1001 : ddr_address1 <= emr | 12'h380; 
          4'b1010 : ddr_address1 <= emr & 12'hc7f;
          default : ddr_address1 <= {`ROW_ADDRESS{1'b0}};
        endcase
      else if ( current_state == PRECHARGE ||
		init_current_state == INIT_PRECHARGE )
        ddr_address1 <= {`ROW_ADDRESS{1'b0}} | 12'h400;
      else if ( current_state == ACTIVE )
        ddr_address1 <= row_address_reg;
      else if ( current_state == BURST_WRITE || current_state == FIRST_WRITE ||
                current_state == BURST_READ )
        ddr_address1 <= column_address_reg1;
      else
        ddr_address1 <= `ROW_ADDRESS'b0;
   end

   always @( negedge clk ) begin
      if ( rst180_r )
        ddr_ba1 <= {{`BANK_ADDRESS-1{1'b0}},1'b0};
      else if ( init_mem )
        case ( init_count )
          4'b0001 : ddr_ba1 <= (`BANK_ADDRESS'b10);
          4'b0010 : ddr_ba1 <= (`BANK_ADDRESS'b11);
          4'b0011 , 4'b1001 , 4'b1010 : ddr_ba1 <= (`BANK_ADDRESS'b01);
          default : ddr_ba1 <= {{`BANK_ADDRESS-1{1'b0}},1'b0};
        endcase
      else if ( current_state == ACTIVE || current_state == FIRST_WRITE ||
                current_state == BURST_WRITE || current_state == BURST_READ)
        ddr_ba1 <= ba_address_reg2;
      else
        ddr_ba1 <= `BANK_ADDRESS'b0;
   end


   always @( negedge clk ) begin
      if ( rst180_r )
        odt_deassert <= 1'b0;
      else if (wrburst_end_3) 
        odt_deassert <= 1'b1;
      else if(!write_cmd3)
        odt_deassert <= 1'b0;
      else
        odt_deassert <= odt_deassert;
   end
   
   assign ddr_odt1 = ( write_cmd3 == 1'b1  && (emr[6]|emr[2]) && !odt_deassert )
			? 1'b1 : 1'b0;  
   
//******************************************************************************
//  Register column address
//******************************************************************************
   always @ (negedge clk) 
      column_address_reg1 <= column_address_reg;

//******************************************************************************
//Pipeline stages for ddr_address and ddr_ba
//******************************************************************************

   always @ (negedge clk) begin
      if (rst180_r == 1'b1) begin
         ddr_odt2  <= 1'b0;
         ddr_rasb2 <= 1'b1;
         ddr_casb2 <= 1'b1;
         ddr_web2  <= 1'b1;
      end
      else begin
         ddr_odt2  <= ddr_odt1;
         ddr_rasb2 <= ddr_rasb1;
         ddr_casb2 <= ddr_casb1;
         ddr_web2  <= ddr_web1;
      end
   end
   
   always @ (negedge clk) begin
      if (rst180_r == 1'b1) 
        ddr_odt_cntrl   <= 1'b0;
      else 
        ddr_odt_cntrl   <= ddr_odt2;
   end

//******************************************************************************
// Control signals to the Memory
//******************************************************************************

   assign ddr_rasb1 = ~((current_state == ACTIVE) || 
			(current_state == PRECHARGE) ||
			(current_state == AUTO_REFRESH) || 
			(init_current_state ==  INIT_PRECHARGE) || 
			(init_current_state == INIT_AUTO_REFRESH)  ||
			(init_current_state == INIT_LOAD_MODE_REG));
   
   assign ddr_casb1 = ~((current_state == BURST_READ) || 
			(current_state == BURST_WRITE)
                        || (current_state == FIRST_WRITE) ||
                        (current_state == AUTO_REFRESH) ||
                        (init_current_state == INIT_AUTO_REFRESH) ||
                        (init_current_state == INIT_LOAD_MODE_REG));
   
   assign ddr_web1  = ~((current_state == BURST_WRITE) || 
			(current_state == FIRST_WRITE) || 
			(current_state == PRECHARGE) ||
			(init_current_state == INIT_PRECHARGE) || 
                        (init_current_state == INIT_LOAD_MODE_REG));

//******************************************************************************
// Register CONTROL SIGNALS outputs
//******************************************************************************

   always @ (negedge clk) begin
      if (rst180_r == 1'b1)
        dqs_div_cascount <= 3'b0;
      else if ((ddr_rasb2 == 1'b1) && (ddr_casb2 == 1'b0) && (ddr_web2 == 1'b1))
	dqs_div_cascount <= burst_cnt_max ;
      else if (dqs_div_cascount != 3'b000)
	dqs_div_cascount <= dqs_div_cascount - 1'b1;
      else
	dqs_div_cascount <= dqs_div_cascount;
   end
   
   always @ (negedge clk) begin
      if (rst180_r == 1'b1)
        dqs_div_rdburstcount <= 3'b000;
      else begin
         if ((dqs_div_cascount == 3'b001) && (burst_length== 3'b010))
           dqs_div_rdburstcount <= 3'b010;
         else if ((dqs_div_cascount == 3'b011) && (burst_length== 3'b011))
           dqs_div_rdburstcount <= 3'b100;
         else begin
            if (dqs_div_rdburstcount != 3'b000)
              dqs_div_rdburstcount <= dqs_div_rdburstcount - 1'b1;
            else
              dqs_div_rdburstcount <= dqs_div_rdburstcount;
         end
      end
   end

   always @ (negedge clk) begin
      if (rst180_r == 1'b1)
        rst_dqs_div_r <= 1'b0;
      else begin
         if (dqs_div_cascount == 3'b001  && burst_length == 3'b010)
           rst_dqs_div_r <= 1'b1;
         else if (dqs_div_cascount == 3'b011  && burst_length == 3'b011)
           rst_dqs_div_r <= 1'b1;
         else if (dqs_div_rdburstcount == 3'b001 && dqs_div_cascount == 3'b000)
           rst_dqs_div_r <= 1'b0;
         else
           rst_dqs_div_r <= rst_dqs_div_r;
      end
   end // always @ (negedge clk)
   
   always @ (negedge clk) 
     rst_dqs_div_r1 <= rst_dqs_div_r;

   always @( negedge clk ) begin
      if(dqs_div_cascount != 3'b0 || dqs_div_rdburstcount != 3'b0 )
        rst_calib <= 1'b1;
      else
        rst_calib <= 1'b0;
   end

   (* IOB = "TRUE" *) FD  rst_iob_out
	    (
	     .Q(rst_dqs_div_int1),
	          .D(rst_dqs_div_r),
	     .C(clk)
	     )/* synthesis syn_useioff = 1 */;

endmodule