ddr2_32mx32_dqs_delay.v

Xilinx DDR2存储器接口调试代码

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005-2007 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor			: Xilinx
// \   \   \/    Version		: $Name: i+IP+131489 $
//  \   \        Application		: MIG
//  /   /        Filename		: ddr2_32Mx32_dqs_delay.v
// /___/   /\    Date Last Modified	: $Date: 2007/09/21 15:23:18 $
// \   \  /  \   Date Created		: Mon May 2 2005
//  \___\/\___\
// Device	: Spartan-3/3A/3A-DSP
// Design Name	: DDR2 SDRAM
// Purpose	: This module generates the delay in the dqs signal.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns/100ps
module ddr2_32Mx32_dqs_delay
  (
   input       clk_in,
   input [4:0] sel_in,
   output      clk_out
   );

   wire delay1;
   wire delay2;
   wire delay3;
   wire delay4;
   wire delay5;

   localparam   HIGH = 1'b1;
   
   LUT4 #
     (
      .INIT (16'hf3c0)
      )
      one 
	(
	 .I0 (HIGH),
	 .I1 (sel_in[4]), 
	 .I2 (delay5), 
	 .I3 (clk_in), 
	 .O  (clk_out)
	 );
 
   LUT4 #
     (
      .INIT (16'hee22)
      ) 
     two 
       (
	.I0 (clk_in), 
	.I1 (sel_in[2]), 
	.I2 (HIGH), 
	.I3 (delay3), 
	.O  (delay4)
	);
   
   LUT4 #
     (
      .INIT (16'he2e2)
      ) 
     three 
       (
	.I0 (clk_in), 
	.I1 (sel_in[0]), 
	.I2 (delay1), 
	.I3 (HIGH), 
	.O  (delay2)
	);
     
   LUT4 #
     (
      .INIT (16'hff00)
      )  
     four 
       (
	.I0 (HIGH), 
	.I1 (HIGH), 
	.I2 (HIGH), 
	.I3 (clk_in), 
	.O (delay1)
	);
   
   LUT4 #
     (
      .INIT (16'hf3c0)
      ) 
     five 
       (
	.I0 (HIGH), 
	.I1 (sel_in[3]), 
	.I2 (delay4), 
	.I3 (clk_in), 
	.O (delay5)
	);
   
   LUT4 #
     (
      .INIT (16'he2e2)
      ) 
     six 
       (
	.I0 (clk_in), 
	.I1 (sel_in[1]), 
	.I2 (delay2), 
	.I3 (HIGH), 
	.O  (delay3)
	);

endmodule