ddr2_32mx32_parameters_0.v

Xilinx DDR2存储器接口调试代码

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005-2007 Xilinx, Inc.
// This	design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /	/\/   /
// /___/  \  /   Vendor			: Xilinx
// \   \   \/    Version		: $Name: i+IP+131489 $
//  \	\        Application		: MIG
//  /	/        Filename		: ddr2_32Mx32_parameters_0.v
// /___/   /\    Date Last Modified	: $Date: 2007/09/21 15:23:18 $
// \   \  /  \   Date Created		: Mon May 2 2005
//  \___\/\___\
// Device	: Spartan-3/3A/3A-DSP
// Design Name	: DDR2 SDRAM
// Purpose	: This module has the parameters used in the design
///////////////////////////////////////////////////////////////////////////////

`define   DATA_WIDTH                               32
`define   DATA_STROBE_WIDTH                        4
`define   DATA_MASK_WIDTH                          4
`define   CLK_WIDTH                                2
`define   CKE_WIDTH                                1
`define   DEEP_MEMORY                              1
`define   ROW_ADDRESS                              13
`define   MEMORY_WIDTH                             8
`define   REGISTERED                               0
`define   COL_AP_WIDTH                             11
`define   DATABITSPERSTROBE                        8
`define   DATABITSPERMASK                          8
`define   NO_OF_CS                                 1
`define   RESET_PORT                               0
`define   DATA_MASK                                1
`define   WRITE_PIPE_ITR                           1
`define   COLUMN_ADDRESS                           10
`define   BANK_ADDRESS                             2
`define   LOAD_MODE_REGISTER                       13'b0010100110011
`define   EXT_LOAD_MODE_REGISTER                   13'b0000001000100
`define   RESET_ACTIVE_LOW                         1'b1
`define   RFC_COUNT_VALUE                          6'b001101
`define   TWR_COUNT_VALUE                          3'b010
`define   MAX_REF_WIDTH                            10
`define   MAX_REF_CNT                        10'b1111000011

`timescale 1ns/100ps