ddr2_32mx32_cal_top.v

来自「Xilinx DDR2存储器接口调试代码」· Verilog 代码 · 共 51 行

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005-2007 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor			: Xilinx
// \   \   \/    Version		: $Name: i+IP+131489 $
//  \   \        Application		: MIG
//  /   /        Filename		: ddr2_32Mx32_cal_top.v
// /___/   /\    Date Last Modified	: $Date: 2007/09/21 15:23:17 $
// \   \  /  \   Date Created		: Mon May 2 2005
//  \___\/\___\
// Device	: Spartan-3/3A/3A-DSP
// Design Name	: DDR2 SDRAM
// Purpose	: This module has the instantiations cal_ctl and tap_dly.
////////////////////////////////////////////////////////////////////////////////

`timescale 1ns/100ps

 module ddr2_32Mx32_cal_top
   (
    input        clk0,
    input        clk0dcmlock,
    input        reset,
    output [4:0] tapfordqs
    );

   wire [31:0] 	 flop2_val;
   wire 	 fpga_rst;
   
   assign 	 fpga_rst = (~reset || ~clk0dcmlock);
   
   ddr2_32Mx32_cal_ctl cal_ctl0 
     (
      .clk       (clk0), 
      .reset     (fpga_rst), 
      .flop2     (flop2_val), 
      .tapfordqs (tapfordqs)
      );
   
   ddr2_32Mx32_tap_dly tap_dly0 
     (
      .clk	(clk0), 
      .reset	(fpga_rst), 
      .tapin	(clk0), 
      .flop2	(flop2_val)
      );

endmodule