ddr2_32mx32_controller_iobs_0.v

Xilinx DDR2存储器接口调试代码

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005-2007 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor		    : Xilinx
// \   \   \/    Version	    : $Name: i+IP+131489 $
//  \   \        Application	    : MIG
//  /   /        Filename	    : ddr2_32Mx32_controller_iobs_0.v
// /___/   /\    Date Last Modified : $Date: 2007/09/21 15:23:17 $
// \   \  /  \   Date Created	    : Mon May 2 2005
//  \___\/\___\
// Device	: Spartan-3/3A/3A-DSP
// Design Name	: DDR2 SDRAM
// Purpose	: This module has the IOB instantiations to address and control 
//		  signals.
///////////////////////////////////////////////////////////////////////////////

`include "../rtl/ddr2_32Mx32_parameters_0.v"
`timescale 1ns/100ps

module ddr2_32Mx32_controller_iobs_0
  (
   input                      clk0,
   input                      ddr_rasb_cntrl,
   input                      ddr_casb_cntrl,
   input                      ddr_web_cntrl,
   input                      ddr_cke_cntrl,
   input                      ddr_csb_cntrl,
   input                      ddr_odt_cntrl,
   input [`ROW_ADDRESS-1:0]   ddr_address_cntrl,
   input [`BANK_ADDRESS-1:0]  ddr_ba_cntrl,
   input                      rst_dqs_div_int,
   output                     ddr_rasb,
   output                     ddr_casb,
   output                     ddr_web,
   output [`BANK_ADDRESS-1:0] ddr_ba,
   output [`ROW_ADDRESS-1:0]  ddr_address,
   output                     ddr_cke,
   output                     ddr_csb,
   output                     ddr_odt0,
   output                     rst_dqs_div,
   input                      rst_dqs_div_in,
   output                     rst_dqs_div_out
   );


   wire                       ddr_odt_reg;
   wire [`ROW_ADDRESS-1:0]    ddr_address_iob_reg;
   wire [`BANK_ADDRESS-1:0]   ddr_ba_reg;
   wire                       ddr_web_q;
   wire                       ddr_rasb_q;
   wire                       ddr_casb_q;
   wire                       ddr_cke_q;
   wire                       ddr_cke_int;

//---- *******************************************  ----
//----  Includes the instantiation of FD for cntrl  ----
//----            signals                           ----
//---- *******************************************  ----

   (* IOB = "TRUE" *) FD iob_web
     (
      .Q (ddr_web_q),
      .D (ddr_web_cntrl),
      .C (~clk0)
      )/* synthesis syn_useioff = 1 */;

   (* IOB = "TRUE" *) FD iob_rasb
     (
      .Q (ddr_rasb_q),
      .D (ddr_rasb_cntrl),
      .C (~clk0)
      )/* synthesis syn_useioff = 1 */;


   (* IOB = "TRUE" *) FD iob_casb
     (
      .Q (ddr_casb_q),
      .D (ddr_casb_cntrl),
      .C (~clk0)
      )/* synthesis syn_useioff = 1 */;


//---- ************************************* ----
//----  Output buffers for control signals   ----
//---- ************************************* ----

   OBUF r16
     (
      .I (ddr_web_q),
      .O (ddr_web)
      );

   OBUF r17
     (
      .I (ddr_rasb_q),
      .O (ddr_rasb)
      );

   OBUF r18
     (
      .I (ddr_casb_q),
      .O (ddr_casb)
      );

   OBUF r19
     (
      .I (ddr_csb_cntrl),
      .O (ddr_csb)
      );


   FD iob_cke1
     (
      .Q (ddr_cke_int),
      .D (ddr_cke_cntrl),
      .C (clk0)
      );


   (* IOB = "TRUE" *) FD iob_cke
     (
      .Q (ddr_cke_q),
      .D (ddr_cke_int),
      .C (~clk0)
      )/* synthesis syn_useioff = 1 */;


   OBUF r20
     ( 
      .I (ddr_cke_q),
      .O (ddr_cke)
      );


  (* IOB = "TRUE" *) FD iob_odt
     (
      .Q (ddr_odt_reg),
      .D (ddr_odt_cntrl),
      .C (~clk0)
      )/* synthesis syn_useioff = 1 */;


   OBUF r21
     (
      .I (ddr_odt_reg),
      .O (ddr_odt0)
      );

//---- *******************************************  ----
//----  Includes the instantiation of FD  and OBUF  ----
//----  for addr signals                            ----
//---- *******************************************  ----    

   genvar addr_i;
   generate 
      for(addr_i = 0; addr_i < `ROW_ADDRESS; addr_i = addr_i + 1)
	begin : gen_addr
	 (* IOB = "TRUE" *) FD FD_inst
	  (
	   .Q (ddr_address_iob_reg[addr_i]),
           .D (ddr_address_cntrl[addr_i]),
           .C (~clk0)
	   )/* synthesis syn_useioff = 1 */;
	 
         OBUF OBUF_inst 
	    (
             .I (ddr_address_iob_reg[addr_i]),
             .O (ddr_address[addr_i])
             );
      end	
   endgenerate
 
   genvar ba_i;
   generate 
      for(ba_i = 0; ba_i < `BANK_ADDRESS; ba_i = ba_i + 1) begin : gen_ba
	 (* IOB = "TRUE" *) FD FD_inst
	  (
           .Q (ddr_ba_reg[ba_i]),
           .D (ddr_ba_cntrl[ba_i]),
           .C (~clk0)
        )/* synthesis syn_useioff = 1 */;

       OBUF OBUF_inst 
         (
          .I (ddr_ba_reg[ba_i]),
          .O (ddr_ba[ba_i])
	  );
      end	
   endgenerate


   IBUF rst_iob_inbuf
     (
      .I (rst_dqs_div_in),
      .O (rst_dqs_div)
      );

   OBUF rst_iob_outbuf
     (
      .I (rst_dqs_div_int),
      .O (rst_dqs_div_out)
      );

endmodule