testlist.hier_info

有用的verilog hdl实验用程序 配有截图

|testlist
list[1] => Decoder0.IN7
list[2] => Decoder0.IN6
list[3] => Decoder0.IN5
list[4] => Decoder0.IN4
list[5] => Decoder0.IN3
list[6] => Decoder0.IN2
list[7] => Decoder0.IN1
list[8] => Decoder0.IN0
result[1] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
result[2] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
result[3] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
result[4] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
result[5] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
result[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
result[7] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
result[8] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE