testlist.v

来自「有用的verilog hdl实验用程序 配有截图」· Verilog 代码 · 共 20 行

module testlist(list,result);
output [8:1] result;
input  [8:1] list;

reg    [8:1] result;

always @(list)
	case(list)
		8'b00000001: result = 1;
		8'b00000010: result = 2;
		8'b00000100: result = 3;
		8'b00001000: result = 4;
		8'b00010000: result = 5;
		8'b00100000: result = 6;
		8'b01000000: result = 7;
		8'b10000000: result = 8;
		default: result = 255;
	endcase

endmodule