rom.vhd

基于vhdl的rom的描述,经过确定测试通过.

library ieee;
use ieee.std_logic_1164.all;
package rom_pack is
subtype rom_word is std_logic_vector(7 downto 0);
subtype rom_range is integer range 0 to 31;
type rom_type is array(rom_range) of rom_word;
constant rom32 :rom_type :=(
    ("00000001"),("10100100"),("10010110"),("00101101"),
    ("11010100"),("01001111"),("00001110"),("01000000"),
    ("11111001"),("00000011"),("10100000"),("10101010"),
    ("11111111"),("00010101"),("10111111"),("00010100"),
    ("11110000"),("01011111"),("00101000"),("10100111"),
    ("10100111"),("01000001"),("00101111"),("00011101"),
    ("11011101"),("01001010"),("00101001"),("10010000"),
    ("00101011"),("00000000"),("11101010"),("11111001"));
end rom_pack;
library ieee;
use ieee.std_logic_1164.all;
use work.rom_pack.all;
entity rom is
generic(read_delay :time);
port(
 addr:in std_logic_vector(4 downto 0);
 clk :in std_logic;
 read :in std_logic;
 dataout :out std_logic_vector(7 downto 0));
end rom;
architecture one of rom is
function logic2int (din :std_logic_vector(4 downto 0)) return rom_range is
 variable result:rom_range :=0;
  begin
   for i in 0 to 4 loop
     if din(i)='1' then
       result:=result+2**i;
     end if;
   end loop;
   return result;
 end function logic2int;
 begin
   process(clk)
    begin
     if clk'event and clk='1' then
       if read='1' then
        dataout<=rom32(logic2int(addr)) after read_delay;
       else 
        dataout<=(others=>'Z') after read_delay;
       end if;
     end if;
   end process;
 end one;