📄 alarm_clock.map.qmsg
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "display_driver display_driver:u6 " "Info: Elaborating entity \"display_driver\" for hierarchy \"display_driver:u6\"" { } { { "ALARM_CLOCK.vhd" "u6" { Text "E:/PLDS/CLOCK/ALARM_CLOCK.vhd" 91 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "display_time DISPLAY_DRIVER.vhd(18) " "Warning (10631): VHDL Process Statement warning at DISPLAY_DRIVER.vhd(18): inferring latch(es) for signal or variable \"display_time\", which holds its previous value in one or more paths through the process" { } { { "DISPLAY_DRIVER.vhd" "" { Text "E:/PLDS/CLOCK/DISPLAY_DRIVER.vhd" 18 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fq_divider fq_divider:u7 " "Info: Elaborating entity \"fq_divider\" for hierarchy \"fq_divider:u7\"" { } { { "ALARM_CLOCK.vhd" "u7" { Text "E:/PLDS/CLOCK/ALARM_CLOCK.vhd" 92 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "led_display led_display:U8 " "Info: Elaborating entity \"led_display\" for hierarchy \"led_display:U8\"" { } { { "ALARM_CLOCK.vhd" "U8" { Text "E:/PLDS/CLOCK/ALARM_CLOCK.vhd" 93 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "displayseg led_display.vhd(21) " "Warning (10492): VHDL Process Statement warning at led_display.vhd(21): signal \"displayseg\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "led_display.vhd" "" { Text "E:/PLDS/CLOCK/led_display.vhd" 21 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "displayseg led_display.vhd(22) " "Warning (10492): VHDL Process Statement warning at led_display.vhd(22): signal \"displayseg\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "led_display.vhd" "" { Text "E:/PLDS/CLOCK/led_display.vhd" 22 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "displayseg led_display.vhd(23) " "Warning (10492): VHDL Process Statement warning at led_display.vhd(23): signal \"displayseg\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "led_display.vhd" "" { Text "E:/PLDS/CLOCK/led_display.vhd" 23 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "displayseg led_display.vhd(24) " "Warning (10492): VHDL Process Statement warning at led_display.vhd(24): signal \"displayseg\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "led_display.vhd" "" { Text "E:/PLDS/CLOCK/led_display.vhd" 24 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "displayseg led_display.vhd(25) " "Warning (10492): VHDL Process Statement warning at led_display.vhd(25): signal \"displayseg\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "led_display.vhd" "" { Text "E:/PLDS/CLOCK/led_display.vhd" 25 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "displayseg led_display.vhd(26) " "Warning (10492): VHDL Process Statement warning at led_display.vhd(26): signal \"displayseg\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "led_display.vhd" "" { Text "E:/PLDS/CLOCK/led_display.vhd" 26 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "displayseg led_display.vhd(27) " "Warning (10492): VHDL Process Statement warning at led_display.vhd(27): signal \"displayseg\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "led_display.vhd" "" { Text "E:/PLDS/CLOCK/led_display.vhd" 27 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "displayseg led_display.vhd(28) " "Warning (10492): VHDL Process Statement warning at led_display.vhd(28): signal \"displayseg\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "led_display.vhd" "" { Text "E:/PLDS/CLOCK/led_display.vhd" 28 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|alarm_clock\|alarm_controller:u3\|curr_state 5 " "Info: State machine \"\|alarm_clock\|alarm_controller:u3\|curr_state\" contains 5 states" { } { { "ALARM_CONTROLLER.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CONTROLLER.vhd" 21 -1 0 } } } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|alarm_clock\|alarm_controller:u3\|curr_state " "Info: Selected Auto state machine encoding method for state machine \"\|alarm_clock\|alarm_controller:u3\|curr_state\"" { } { { "ALARM_CONTROLLER.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CONTROLLER.vhd" 21 -1 0 } } } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|alarm_clock\|alarm_controller:u3\|curr_state " "Info: Encoding result for state machine \"\|alarm_clock\|alarm_controller:u3\|curr_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "alarm_controller:u3\|curr_state.s4 " "Info: Encoded state bit \"alarm_controller:u3\|curr_state.s4\"" { } { { "ALARM_CONTROLLER.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CONTROLLER.vhd" 21 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "alarm_controller:u3\|curr_state.s3 " "Info: Encoded state bit \"alarm_controller:u3\|curr_state.s3\"" { } { { "ALARM_CONTROLLER.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CONTROLLER.vhd" 21 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "alarm_controller:u3\|curr_state.s2 " "Info: Encoded state bit \"alarm_controller:u3\|curr_state.s2\"" { } { { "ALARM_CONTROLLER.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CONTROLLER.vhd" 21 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "alarm_controller:u3\|curr_state.s1 " "Info: Encoded state bit \"alarm_controller:u3\|curr_state.s1\"" { } { { "ALARM_CONTROLLER.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CONTROLLER.vhd" 21 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "alarm_controller:u3\|curr_state.s0 " "Info: Encoded state bit \"alarm_controller:u3\|curr_state.s0\"" { } { { "ALARM_CONTROLLER.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CONTROLLER.vhd" 21 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} } { } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|alarm_clock\|alarm_controller:u3\|curr_state.s0 00000 " "Info: State \"\|alarm_clock\|alarm_controller:u3\|curr_state.s0\" uses code string \"00000\"" { } { { "ALARM_CONTROLLER.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CONTROLLER.vhd" 21 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|alarm_clock\|alarm_controller:u3\|curr_state.s1 00011 " "Info: State \"\|alarm_clock\|alarm_controller:u3\|curr_state.s1\" uses code string \"00011\"" { } { { "ALARM_CONTROLLER.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CONTROLLER.vhd" 21 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|alarm_clock\|alarm_controller:u3\|curr_state.s2 00101 " "Info: State \"\|alarm_clock\|alarm_controller:u3\|curr_state.s2\" uses code string \"00101\"" { } { { "ALARM_CONTROLLER.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CONTROLLER.vhd" 21 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|alarm_clock\|alarm_controller:u3\|curr_state.s3 01001 " "Info: State \"\|alarm_clock\|alarm_controller:u3\|curr_state.s3\" uses code string \"01001\"" { } { { "ALARM_CONTROLLER.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CONTROLLER.vhd" 21 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|alarm_clock\|alarm_controller:u3\|curr_state.s4 10001 " "Info: State \"\|alarm_clock\|alarm_controller:u3\|curr_state.s4\" uses code string \"10001\"" { } { { "ALARM_CONTROLLER.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CONTROLLER.vhd" 21 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} } { { "ALARM_CONTROLLER.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CONTROLLER.vhd" 21 -1 0 } } } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "370 " "Info: Implemented 370 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "15 " "Info: Implemented 15 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "347 " "Info: Implemented 347 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "156 " "Info: Allocated 156 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue May 13 23:39:30 2008 " "Info: Processing ended: Tue May 13 23:39:30 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
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