key_buffer.vhd

来自「可以调整时间和设置闹钟的数字钟(VHDL)」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;
use work.p_alarm.all;
entity key_buffer is
	port(key: in t_digital;
		clk: in std_logic;
		reset: in std_logic;
		new_time: out t_clock_time);
end key_buffer;

architecture art of key_buffer is
	signal n_t: t_clock_time;
	begin
		shift: process(reset,clk) is 
		begin
			if(reset='1') then
				n_t<=(0,0,0,0,0,0);
			elsif (clk'event and clk='1') then
				for i in 5 downto 1 loop
					n_t(i)<=n_t(i-1);
				end loop;
				n_t(0)<=key;
			end if;
		end process;
		new_time<=n_t;
end art;