led_display.vhd

可以调整时间和设置闹钟的数字钟(VHDL)

library ieee;
use ieee.std_logic_1164.all;
use work.p_alarm.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity led_display is
	port (	displayseg: t_display;
			clk		: in std_logic;
			clock_out: out std_logic_vector (6 downto 0)
		);
end entity led_display;

architecture led_display_arch of led_display is
	signal   cnt8 :  std_logic_vector (2 downto 0);
	signal dispval: std_logic_vector(6 downto 0);
begin
	p1:process(cnt8)
		begin
		case cnt8 is
			when "000" => dispval<=displayseg(0);
			when "001" => dispval<=displayseg(1);
			when "010" => dispval<=displayseg(2);
			when "011" => dispval<=displayseg(3);
			when "100" => dispval<=displayseg(4);
			when "101" => dispval<=displayseg(5);
			when "110" => dispval<=displayseg(6);
			when "111" => dispval<=displayseg(7);
			WHEN OTHERS =>NULL;
		end case;
	end process p1;
	p2: process(clk)
		begin
			if(clk'event and clk = '1') then
				clock_out<=dispval;
				if(cnt8="111") then
					cnt8<="000";
				else
					cnt8 <= cnt8 + 1;
			    end if;
			end if;
	end process p2;
	
end led_display_arch;