spi_master.map.summary

来自「AN485_CH-MAX II CPLD 中的串行外设接口主机（verilog 」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Thu Nov 22 16:41:54 2007
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : SPI_Master
Top-level Entity Name : SPI_Master
Family : MAX II
Total logic elements : 78
Total pins : 25
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0