decoder7.vhd

来自「这个是我毕业设计的最初方案 8位二进制密码锁」· VHDL 代码 · 共 30 行

library ieee;
use ieee.std_logic_1164.all;
entity decoder7 is
port(bcd:in std_logic_vector(3 downto 0);
     dout:out std_logic_vector(6 downto 0));
end decoder7;
architecture rtl of decoder7 is
begin
  process(bcd)
    begin
      case bcd is
        when "0000"=>dout<="0111111";
        when "0001"=>dout<="0000110";
        when "0010"=>dout<="1011011";
        when "0011"=>dout<="1001111";
        when "0100"=>dout<="1100110";
        when "0101"=>dout<="1101101";
        when "0110"=>dout<="1111101";
        when "0111"=>dout<="0000111";
        when "1000"=>dout<="1111111";
        when "1001"=>dout<="1101111";
        when "1010"=>dout<="1110111";
        when "1011"=>dout<="1111001";
        when "1100"=>dout<="0111100";
        when "1101"=>dout<="1011011";
        when "1110"=>dout<="1111100";
        when "1111"=>dout<="1110100";
      end case;
    end process;
end rtl;