fir.fit.qmsg

我自己用VHDL语言编的16阶FIR数字滤波器

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Info: Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "7.082 ns register register " "Info: Estimated most critical path is register to register delay of 7.082 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns add9910:inst3\|Dout\[1\] 1 REG LAB_X17_Y5 20 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X17_Y5; Fanout = 20; REG Node = 'add9910:inst3\|Dout\[1\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { add9910:inst3|Dout[1] } "NODE_NAME" } } { "add9910.vhd" "" { Text "G:/vhdltext/fir/add9910.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.198 ns) + CELL(0.333 ns) 1.531 ns mult29:inst27\|Add3~224COUT1_226 2 COMB LAB_X12_Y5 2 " "Info: 2: + IC(1.198 ns) + CELL(0.333 ns) = 1.531 ns; Loc. = LAB_X12_Y5; Fanout = 2; COMB Node = 'mult29:inst27\|Add3~224COUT1_226'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.531 ns" { add9910:inst3|Dout[1] mult29:inst27|Add3~224COUT1_226 } "NODE_NAME" } } { "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.468 ns) 1.999 ns mult29:inst27\|Add3~221 3 COMB LAB_X12_Y5 3 " "Info: 3: + IC(0.000 ns) + CELL(0.468 ns) = 1.999 ns; Loc. = LAB_X12_Y5; Fanout = 3; COMB Node = 'mult29:inst27\|Add3~221'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.468 ns" { mult29:inst27|Add3~224COUT1_226 mult29:inst27|Add3~221 } "NODE_NAME" } } { "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.801 ns) + CELL(0.443 ns) 3.243 ns mult29:inst27\|Add4~244COUT1_252 4 COMB LAB_X15_Y5 2 " "Info: 4: + IC(0.801 ns) + CELL(0.443 ns) = 3.243 ns; Loc. = LAB_X15_Y5; Fanout = 2; COMB Node = 'mult29:inst27\|Add4~244COUT1_252'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.244 ns" { mult29:inst27|Add3~221 mult29:inst27|Add4~244COUT1_252 } "NODE_NAME" } } { "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 3.305 ns mult29:inst27\|Add4~242COUT1_253 5 COMB LAB_X15_Y5 2 " "Info: 5: + IC(0.000 ns) + CELL(0.062 ns) = 3.305 ns; Loc. = LAB_X15_Y5; Fanout = 2; COMB Node = 'mult29:inst27\|Add4~242COUT1_253'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.062 ns" { mult29:inst27|Add4~244COUT1_252 mult29:inst27|Add4~242COUT1_253 } "NODE_NAME" } } { "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.468 ns) 3.773 ns mult29:inst27\|Add4~239 6 COMB LAB_X15_Y5 1 " "Info: 6: + IC(0.000 ns) + CELL(0.468 ns) = 3.773 ns; Loc. = LAB_X15_Y5; Fanout = 1; COMB Node = 'mult29:inst27\|Add4~239'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.468 ns" { mult29:inst27|Add4~242COUT1_253 mult29:inst27|Add4~239 } "NODE_NAME" } } { "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.584 ns) + CELL(0.454 ns) 4.811 ns mult29:inst27\|Add1~370 7 COMB LAB_X15_Y6 2 " "Info: 7: + IC(0.584 ns) + CELL(0.454 ns) = 4.811 ns; Loc. = LAB_X15_Y6; Fanout = 2; COMB Node = 'mult29:inst27\|Add1~370'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.038 ns" { mult29:inst27|Add4~239 mult29:inst27|Add1~370 } "NODE_NAME" } } { "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.830 ns) + CELL(0.645 ns) 6.286 ns mult29:inst27\|Dout\[6\]~61 8 COMB LAB_X16_Y5 6 " "Info: 8: + IC(0.830 ns) + CELL(0.645 ns) = 6.286 ns; Loc. = LAB_X16_Y5; Fanout = 6; COMB Node = 'mult29:inst27\|Dout\[6\]~61'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.475 ns" { mult29:inst27|Add1~370 mult29:inst27|Dout[6]~61 } "NODE_NAME" } } { "mult29.vhd" "" { Text "G:/vhdltext/fir/mult29.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.105 ns) 6.391 ns mult29:inst27\|Dout\[11\]~56 9 COMB LAB_X16_Y4 1 " "Info: 9: + IC(0.000 ns) + CELL(0.105 ns) = 6.391 ns; Loc. = LAB_X16_Y4; Fanout = 1; COMB Node = 'mult29:inst27\|Dout\[11\]~56'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.105 ns" { mult29:inst27|Dout[6]~61 mult29:inst27|Dout[11]~56 } "NODE_NAME" } } { "mult29.vhd" "" { Text "G:/vhdltext/fir/mult29.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.691 ns) 7.082 ns mult29:inst27\|Dout\[12\] 10 REG LAB_X16_Y4 3 " "Info: 10: + IC(0.000 ns) + CELL(0.691 ns) = 7.082 ns; Loc. = LAB_X16_Y4; Fanout = 3; REG Node = 'mult29:inst27\|Dout\[12\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.691 ns" { mult29:inst27|Dout[11]~56 mult29:inst27|Dout[12] } "NODE_NAME" } } { "mult29.vhd" "" { Text "G:/vhdltext/fir/mult29.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.669 ns ( 51.81 % ) " "Info: Total cell delay = 3.669 ns ( 51.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.413 ns ( 48.19 % ) " "Info: Total interconnect delay = 3.413 ns ( 48.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.082 ns" { add9910:inst3|Dout[1] mult29:inst27|Add3~224COUT1_226 mult29:inst27|Add3~221 mult29:inst27|Add4~244COUT1_252 mult29:inst27|Add4~242COUT1_253 mult29:inst27|Add4~239 mult29:inst27|Add1~370 mult29:inst27|Dout[6]~61 mult29:inst27|Dout[11]~56 mult29:inst27|Dout[12] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "6 7 " "Info: Average interconnect usage is 6% of the available device resources. Peak interconnect usage is 7%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x14_y0 x27_y14 " "Info: The peak interconnect region extends from location x14_y0 to location x27_y14" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:03 " "Info: Fitter routing operations ending: elapsed time is 00:00:03" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat May 03 12:07:05 2008 " "Info: Processing ended: Sat May 03 12:07:05 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:20 " "Info: Elapsed time: 00:00:20" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "G:/vhdltext/fir/fir.fit.smsg " "Info: Generated suppressed messages file G:/vhdltext/fir/fir.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}