fir.tan.qmsg

我自己用VHDL语言编的16阶FIR数字滤波器

{ "Info" "ITDB_FULL_TCO_RESULT" "clk Dout\[9\] add151710:inst19\|Dout\[9\] 6.265 ns register " "Info: tco from clock \"clk\" to destination pin \"Dout\[9\]\" through register \"add151710:inst19\|Dout\[9\]\" is 6.265 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.139 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.139 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 329 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 329; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 128 408 576 144 "clk" "" } { 144 2056 2088 160 "clk" "" } { 152 2288 2320 168 "clk" "" } { 144 1616 1648 160 "clk" "" } { 144 1392 1424 160 "clk" "" } { 136 1144 1176 152 "clk" "" } { 136 936 960 152 "clk" "" } { 376 2280 2304 392 "clk" "" } { 376 2544 2568 392 "clk" "" } { 368 2000 2024 384 "clk" "" } { 360 1688 1712 376 "clk" "" } { 360 1440 1464 376 "clk" "" } { 360 1152 1176 376 "clk" "" } { 360 864 896 376 "clk" "" } { 360 608 640 376 "clk" "" } { 756 360 376 784 "clk" "" } { 752 696 712 784 "clk" "" } { 752 968 984 784 "clk" "" } { 744 1256 1272 776 "clk" "" } { 760 1792 1808 792 "clk" "" } { 752 2064 2080 784 "clk" "" } { 760 2320 2336 800 "clk" "" } { 1024 416 440 1040 "clk" "" } { 1016 1016 1032 1032 "clk" "" } { 744 1496 1512 784 "clk" "" } { 1032 1536 1552 1048 "clk" "" } { 1224 656 688 1240 "clk" "" } { 1192 1784 1808 1208 "clk" "" } { 1292 1336 1352 1320 "clk" "" } { 1032 2128 2152 1048 "clk" "" } { 616 904 928 632 "clk" "" } { 600 1168 1190 616 "clk" "" } { 600 1424 1456 616 "clk" "" } { 616 1728 1750 632 "clk" "" } { 616 1968 1992 632 "clk" "" } { 648 2240 2264 664 "clk" "" } { 616 2488 2520 632 "clk" "" } { 144 1840 1872 160 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.547 ns) 2.139 ns add151710:inst19\|Dout\[9\] 2 REG LC_X17_Y10_N9 1 " "Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X17_Y10_N9; Fanout = 1; REG Node = 'add151710:inst19\|Dout\[9\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.009 ns" { clk add151710:inst19|Dout[9] } "NODE_NAME" } } { "add151710.vhd" "" { Text "G:/vhdltext/fir/add151710.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.40 % ) " "Info: Total cell delay = 1.677 ns ( 78.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.462 ns ( 21.60 % ) " "Info: Total interconnect delay = 0.462 ns ( 21.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.139 ns" { clk add151710:inst19|Dout[9] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 add151710:inst19|Dout[9] } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "add151710.vhd" "" { Text "G:/vhdltext/fir/add151710.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.953 ns + Longest register pin " "Info: + Longest register to pin delay is 3.953 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns add151710:inst19\|Dout\[9\] 1 REG LC_X17_Y10_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y10_N9; Fanout = 1; REG Node = 'add151710:inst19\|Dout\[9\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { add151710:inst19|Dout[9] } "NODE_NAME" } } { "add151710.vhd" "" { Text "G:/vhdltext/fir/add151710.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.331 ns) + CELL(1.622 ns) 3.953 ns Dout\[9\] 2 PIN PIN_36 0 " "Info: 2: + IC(2.331 ns) + CELL(1.622 ns) = 3.953 ns; Loc. = PIN_36; Fanout = 0; PIN Node = 'Dout\[9\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.953 ns" { add151710:inst19|Dout[9] Dout[9] } "NODE_NAME" } } { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 1488 1608 1784 1504 "Dout\[9..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns ( 41.03 % ) " "Info: Total cell delay = 1.622 ns ( 41.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.331 ns ( 58.97 % ) " "Info: Total interconnect delay = 2.331 ns ( 58.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.953 ns" { add151710:inst19|Dout[9] Dout[9] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "3.953 ns" { add151710:inst19|Dout[9] Dout[9] } { 0.000ns 2.331ns } { 0.000ns 1.622ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.139 ns" { clk add151710:inst19|Dout[9] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 add151710:inst19|Dout[9] } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.953 ns" { add151710:inst19|Dout[9] Dout[9] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "3.953 ns" { add151710:inst19|Dout[9] Dout[9] } { 0.000ns 2.331ns } { 0.000ns 1.622ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "dff9:inst\|Dout\[1\] Din\[1\] clk -2.892 ns register " "Info: th for register \"dff9:inst\|Dout\[1\]\" (data pin = \"Din\[1\]\", clock pin = \"clk\") is -2.892 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.139 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.139 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 329 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 329; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 128 408 576 144 "clk" "" } { 144 2056 2088 160 "clk" "" } { 152 2288 2320 168 "clk" "" } { 144 1616 1648 160 "clk" "" } { 144 1392 1424 160 "clk" "" } { 136 1144 1176 152 "clk" "" } { 136 936 960 152 "clk" "" } { 376 2280 2304 392 "clk" "" } { 376 2544 2568 392 "clk" "" } { 368 2000 2024 384 "clk" "" } { 360 1688 1712 376 "clk" "" } { 360 1440 1464 376 "clk" "" } { 360 1152 1176 376 "clk" "" } { 360 864 896 376 "clk" "" } { 360 608 640 376 "clk" "" } { 756 360 376 784 "clk" "" } { 752 696 712 784 "clk" "" } { 752 968 984 784 "clk" "" } { 744 1256 1272 776 "clk" "" } { 760 1792 1808 792 "clk" "" } { 752 2064 2080 784 "clk" "" } { 760 2320 2336 800 "clk" "" } { 1024 416 440 1040 "clk" "" } { 1016 1016 1032 1032 "clk" "" } { 744 1496 1512 784 "clk" "" } { 1032 1536 1552 1048 "clk" "" } { 1224 656 688 1240 "clk" "" } { 1192 1784 1808 1208 "clk" "" } { 1292 1336 1352 1320 "clk" "" } { 1032 2128 2152 1048 "clk" "" } { 616 904 928 632 "clk" "" } { 600 1168 1190 616 "clk" "" } { 600 1424 1456 616 "clk" "" } { 616 1728 1750 632 "clk" "" } { 616 1968 1992 632 "clk" "" } { 648 2240 2264 664 "clk" "" } { 616 2488 2520 632 "clk" "" } { 144 1840 1872 160 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.547 ns) 2.139 ns dff9:inst\|Dout\[1\] 2 REG LC_X23_Y7_N4 1 " "Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X23_Y7_N4; Fanout = 1; REG Node = 'dff9:inst\|Dout\[1\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.009 ns" { clk dff9:inst|Dout[1] } "NODE_NAME" } } { "dff9.vhd" "" { Text "G:/vhdltext/fir/dff9.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.40 % ) " "Info: Total cell delay = 1.677 ns ( 78.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.462 ns ( 21.60 % ) " "Info: Total interconnect delay = 0.462 ns ( 21.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.139 ns" { clk dff9:inst|Dout[1] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 dff9:inst|Dout[1] } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "dff9.vhd" "" { Text "G:/vhdltext/fir/dff9.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.043 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.043 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns Din\[1\] 1 PIN PIN_65 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_65; Fanout = 1; PIN Node = 'Din\[1\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Din[1] } "NODE_NAME" } } { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 192 408 576 208 "Din\[8..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.824 ns) + CELL(0.089 ns) 5.043 ns dff9:inst\|Dout\[1\] 2 REG LC_X23_Y7_N4 1 " "Info: 2: + IC(3.824 ns) + CELL(0.089 ns) = 5.043 ns; Loc. = LC_X23_Y7_N4; Fanout = 1; REG Node = 'dff9:inst\|Dout\[1\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.913 ns" { Din[1] dff9:inst|Dout[1] } "NODE_NAME" } } { "dff9.vhd" "" { Text "G:/vhdltext/fir/dff9.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.219 ns ( 24.17 % ) " "Info: Total cell delay = 1.219 ns ( 24.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.824 ns ( 75.83 % ) " "Info: Total interconnect delay = 3.824 ns ( 75.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.043 ns" { Din[1] dff9:inst|Dout[1] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "5.043 ns" { Din[1] Din[1]~out0 dff9:inst|Dout[1] } { 0.000ns 0.000ns 3.824ns } { 0.000ns 1.130ns 0.089ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.139 ns" { clk dff9:inst|Dout[1] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 dff9:inst|Dout[1] } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.043 ns" { Din[1] dff9:inst|Dout[1] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "5.043 ns" { Din[1] Din[1]~out0 dff9:inst|Dout[1] } { 0.000ns 0.000ns 3.824ns } { 0.000ns 1.130ns 0.089ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat May 03 12:11:43 2008 " "Info: Processing ended: Sat May 03 12:11:43 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}