📄 fir.tan.qmsg

📁 我自己用VHDL语言编的16阶FIR数字滤波器
💻 QMSG
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{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 128 408 576 144 "clk" "" } { 144 2056 2088 160 "clk" "" } { 152 2288 2320 168 "clk" "" } { 144 1616 1648 160 "clk" "" } { 144 1392 1424 160 "clk" "" } { 136 1144 1176 152 "clk" "" } { 136 936 960 152 "clk" "" } { 376 2280 2304 392 "clk" "" } { 376 2544 2568 392 "clk" "" } { 368 2000 2024 384 "clk" "" } { 360 1688 1712 376 "clk" "" } { 360 1440 1464 376 "clk" "" } { 360 1152 1176 376 "clk" "" } { 360 864 896 376 "clk" "" } { 360 608 640 376 "clk" "" } { 756 360 376 784 "clk" "" } { 752 696 712 784 "clk" "" } { 752 968 984 784 "clk" "" } { 744 1256 1272 776 "clk" "" } { 760 1792 1808 792 "clk" "" } { 752 2064 2080 784 "clk" "" } { 760 2320 2336 800 "clk" "" } { 1024 416 440 1040 "clk" "" } { 1016 1016 1032 1032 "clk" "" } { 744 1496 1512 784 "clk" "" } { 1032 1536 1552 1048 "clk" "" } { 1224 656 688 1240 "clk" "" } { 1192 1784 1808 1208 "clk" "" } { 1292 1336 1352 1320 "clk" "" } { 1032 2128 2152 1048 "clk" "" } { 616 904 928 632 "clk" "" } { 600 1168 1190 616 "clk" "" } { 600 1424 1456 616 "clk" "" } { 616 1728 1750 632 "clk" "" } { 616 1968 1992 632 "clk" "" } { 648 2240 2264 664 "clk" "" } { 616 2488 2520 632 "clk" "" } { 144 1840 1872 160 "clk" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register add9910:inst3\|Dout\[0\] register mult29:inst27\|Dout\[12\] 134.95 MHz 7.41 ns Internal " "Info: Clock \"clk\" has Internal fmax of 134.95 MHz between source register \"add9910:inst3\|Dout\[0\]\" and destination register \"mult29:inst27\|Dout\[12\]\" (period= 7.41 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.208 ns + Longest register register " "Info: + Longest register to register delay is 7.208 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns add9910:inst3\|Dout\[0\] 1 REG LC_X17_Y5_N0 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y5_N0; Fanout = 15; REG Node = 'add9910:inst3\|Dout\[0\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { add9910:inst3|Dout[0] } "NODE_NAME" } } { "add9910.vhd" "" { Text "G:/vhdltext/fir/add9910.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.273 ns) + CELL(0.443 ns) 1.716 ns mult29:inst27\|Add3~224COUT1_226 2 COMB LC_X12_Y5_N0 2 " "Info: 2: + IC(1.273 ns) + CELL(0.443 ns) = 1.716 ns; Loc. = LC_X12_Y5_N0; Fanout = 2; COMB Node = 'mult29:inst27\|Add3~224COUT1_226'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.716 ns" { add9910:inst3|Dout[0] mult29:inst27|Add3~224COUT1_226 } "NODE_NAME" } } { "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.468 ns) 2.184 ns mult29:inst27\|Add3~221 3 COMB LC_X12_Y5_N1 3 " "Info: 3: + IC(0.000 ns) + CELL(0.468 ns) = 2.184 ns; Loc. = LC_X12_Y5_N1; Fanout = 3; COMB Node = 'mult29:inst27\|Add3~221'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.468 ns" { mult29:inst27|Add3~224COUT1_226 mult29:inst27|Add3~221 } "NODE_NAME" } } { "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.951 ns) + CELL(0.333 ns) 3.468 ns mult29:inst27\|Add4~244COUT1_252 4 COMB LC_X15_Y5_N7 2 " "Info: 4: + IC(0.951 ns) + CELL(0.333 ns) = 3.468 ns; Loc. = LC_X15_Y5_N7; Fanout = 2; COMB Node = 'mult29:inst27\|Add4~244COUT1_252'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.284 ns" { mult29:inst27|Add3~221 mult29:inst27|Add4~244COUT1_252 } "NODE_NAME" } } { "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 3.530 ns mult29:inst27\|Add4~242COUT1_253 5 COMB LC_X15_Y5_N8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.062 ns) = 3.530 ns; Loc. = LC_X15_Y5_N8; Fanout = 2; COMB Node = 'mult29:inst27\|Add4~242COUT1_253'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.062 ns" { mult29:inst27|Add4~244COUT1_252 mult29:inst27|Add4~242COUT1_253 } "NODE_NAME" } } { "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.468 ns) 3.998 ns mult29:inst27\|Add4~239 6 COMB LC_X15_Y5_N9 1 " "Info: 6: + IC(0.000 ns) + CELL(0.468 ns) = 3.998 ns; Loc. = LC_X15_Y5_N9; Fanout = 1; COMB Node = 'mult29:inst27\|Add4~239'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.468 ns" { mult29:inst27|Add4~242COUT1_253 mult29:inst27|Add4~239 } "NODE_NAME" } } { "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.930 ns) + CELL(0.088 ns) 5.016 ns mult29:inst27\|Add1~370 7 COMB LC_X15_Y6_N8 2 " "Info: 7: + IC(0.930 ns) + CELL(0.088 ns) = 5.016 ns; Loc. = LC_X15_Y6_N8; Fanout = 2; COMB Node = 'mult29:inst27\|Add1~370'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.018 ns" { mult29:inst27|Add4~239 mult29:inst27|Add1~370 } "NODE_NAME" } } { "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.908 ns) + CELL(0.533 ns) 6.457 ns mult29:inst27\|Dout\[6\]~61 8 COMB LC_X16_Y5_N9 6 " "Info: 8: + IC(0.908 ns) + CELL(0.533 ns) = 6.457 ns; Loc. = LC_X16_Y5_N9; Fanout = 6; COMB Node = 'mult29:inst27\|Dout\[6\]~61'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.441 ns" { mult29:inst27|Add1~370 mult29:inst27|Dout[6]~61 } "NODE_NAME" } } { "mult29.vhd" "" { Text "G:/vhdltext/fir/mult29.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.105 ns) 6.562 ns mult29:inst27\|Dout\[11\]~56 9 COMB LC_X16_Y4_N4 1 " "Info: 9: + IC(0.000 ns) + CELL(0.105 ns) = 6.562 ns; Loc. = LC_X16_Y4_N4; Fanout = 1; COMB Node = 'mult29:inst27\|Dout\[11\]~56'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.105 ns" { mult29:inst27|Dout[6]~61 mult29:inst27|Dout[11]~56 } "NODE_NAME" } } { "mult29.vhd" "" { Text "G:/vhdltext/fir/mult29.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.646 ns) 7.208 ns mult29:inst27\|Dout\[12\] 10 REG LC_X16_Y4_N5 3 " "Info: 10: + IC(0.000 ns) + CELL(0.646 ns) = 7.208 ns; Loc. = LC_X16_Y4_N5; Fanout = 3; REG Node = 'mult29:inst27\|Dout\[12\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.646 ns" { mult29:inst27|Dout[11]~56 mult29:inst27|Dout[12] } "NODE_NAME" } } { "mult29.vhd" "" { Text "G:/vhdltext/fir/mult29.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.146 ns ( 43.65 % ) " "Info: Total cell delay = 3.146 ns ( 43.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.062 ns ( 56.35 % ) " "Info: Total interconnect delay = 4.062 ns ( 56.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.208 ns" { add9910:inst3|Dout[0] mult29:inst27|Add3~224COUT1_226 mult29:inst27|Add3~221 mult29:inst27|Add4~244COUT1_252 mult29:inst27|Add4~242COUT1_253 mult29:inst27|Add4~239 mult29:inst27|Add1~370 mult29:inst27|Dout[6]~61 mult29:inst27|Dout[11]~56 mult29:inst27|Dout[12] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.208 ns" { add9910:inst3|Dout[0] mult29:inst27|Add3~224COUT1_226 mult29:inst27|Add3~221 mult29:inst27|Add4~244COUT1_252 mult29:inst27|Add4~242COUT1_253 mult29:inst27|Add4~239 mult29:inst27|Add1~370 mult29:inst27|Dout[6]~61 mult29:inst27|Dout[11]~56 mult29:inst27|Dout[12] } { 0.000ns 1.273ns 0.000ns 0.951ns 0.000ns 0.000ns 0.930ns 0.908ns 0.000ns 0.000ns } { 0.000ns 0.443ns 0.468ns 0.333ns 0.062ns 0.468ns 0.088ns 0.533ns 0.105ns 0.646ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.110 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.110 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 329 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 329; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 128 408 576 144 "clk" "" } { 144 2056 2088 160 "clk" "" } { 152 2288 2320 168 "clk" "" } { 144 1616 1648 160 "clk" "" } { 144 1392 1424 160 "clk" "" } { 136 1144 1176 152 "clk" "" } { 136 936 960 152 "clk" "" } { 376 2280 2304 392 "clk" "" } { 376 2544 2568 392 "clk" "" } { 368 2000 2024 384 "clk" "" } { 360 1688 1712 376 "clk" "" } { 360 1440 1464 376 "clk" "" } { 360 1152 1176 376 "clk" "" } { 360 864 896 376 "clk" "" } { 360 608 640 376 "clk" "" } { 756 360 376 784 "clk" "" } { 752 696 712 784 "clk" "" } { 752 968 984 784 "clk" "" } { 744 1256 1272 776 "clk" "" } { 760 1792 1808 792 "clk" "" } { 752 2064 2080 784 "clk" "" } { 760 2320 2336 800 "clk" "" } { 1024 416 440 1040 "clk" "" } { 1016 1016 1032 1032 "clk" "" } { 744 1496 1512 784 "clk" "" } { 1032 1536 1552 1048 "clk" "" } { 1224 656 688 1240 "clk" "" } { 1192 1784 1808 1208 "clk" "" } { 1292 1336 1352 1320 "clk" "" } { 1032 2128 2152 1048 "clk" "" } { 616 904 928 632 "clk" "" } { 600 1168 1190 616 "clk" "" } { 600 1424 1456 616 "clk" "" } { 616 1728 1750 632 "clk" "" } { 616 1968 1992 632 "clk" "" } { 648 2240 2264 664 "clk" "" } { 616 2488 2520 632 "clk" "" } { 144 1840 1872 160 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.547 ns) 2.110 ns mult29:inst27\|Dout\[12\] 2 REG LC_X16_Y4_N5 3 " "Info: 2: + IC(0.433 ns) + CELL(0.547 ns) = 2.110 ns; Loc. = LC_X16_Y4_N5; Fanout = 3; REG Node = 'mult29:inst27\|Dout\[12\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.980 ns" { clk mult29:inst27|Dout[12] } "NODE_NAME" } } { "mult29.vhd" "" { Text "G:/vhdltext/fir/mult29.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 79.48 % ) " "Info: Total cell delay = 1.677 ns ( 79.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.433 ns ( 20.52 % ) " "Info: Total interconnect delay = 0.433 ns ( 20.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.110 ns" { clk mult29:inst27|Dout[12] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.110 ns" { clk clk~out0 mult29:inst27|Dout[12] } { 0.000ns 0.000ns 0.433ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.110 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.110 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 329 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 329; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 128 408 576 144 "clk" "" } { 144 2056 2088 160 "clk" "" } { 152 2288 2320 168 "clk" "" } { 144 1616 1648 160 "clk" "" } { 144 1392 1424 160 "clk" "" } { 136 1144 1176 152 "clk" "" } { 136 936 960 152 "clk" "" } { 376 2280 2304 392 "clk" "" } { 376 2544 2568 392 "clk" "" } { 368 2000 2024 384 "clk" "" } { 360 1688 1712 376 "clk" "" } { 360 1440 1464 376 "clk" "" } { 360 1152 1176 376 "clk" "" } { 360 864 896 376 "clk" "" } { 360 608 640 376 "clk" "" } { 756 360 376 784 "clk" "" } { 752 696 712 784 "clk" "" } { 752 968 984 784 "clk" "" } { 744 1256 1272 776 "clk" "" } { 760 1792 1808 792 "clk" "" } { 752 2064 2080 784 "clk" "" } { 760 2320 2336 800 "clk" "" } { 1024 416 440 1040 "clk" "" } { 1016 1016 1032 1032 "clk" "" } { 744 1496 1512 784 "clk" "" } { 1032 1536 1552 1048 "clk" "" } { 1224 656 688 1240 "clk" "" } { 1192 1784 1808 1208 "clk" "" } { 1292 1336 1352 1320 "clk" "" } { 1032 2128 2152 1048 "clk" "" } { 616 904 928 632 "clk" "" } { 600 1168 1190 616 "clk" "" } { 600 1424 1456 616 "clk" "" } { 616 1728 1750 632 "clk" "" } { 616 1968 1992 632 "clk" "" } { 648 2240 2264 664 "clk" "" } { 616 2488 2520 632 "clk" "" } { 144 1840 1872 160 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.547 ns) 2.110 ns add9910:inst3\|Dout\[0\] 2 REG LC_X17_Y5_N0 15 " "Info: 2: + IC(0.433 ns) + CELL(0.547 ns) = 2.110 ns; Loc. = LC_X17_Y5_N0; Fanout = 15; REG Node = 'add9910:inst3\|Dout\[0\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.980 ns" { clk add9910:inst3|Dout[0] } "NODE_NAME" } } { "add9910.vhd" "" { Text "G:/vhdltext/fir/add9910.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 79.48 % ) " "Info: Total cell delay = 1.677 ns ( 79.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.433 ns ( 20.52 % ) " "Info: Total interconnect delay = 0.433 ns ( 20.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.110 ns" { clk add9910:inst3|Dout[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.110 ns" { clk clk~out0 add9910:inst3|Dout[0] } { 0.000ns 0.000ns 0.433ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.110 ns" { clk mult29:inst27|Dout[12] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.110 ns" { clk clk~out0 mult29:inst27|Dout[12] } { 0.000ns 0.000ns 0.433ns } { 0.000ns 1.130ns 0.547ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.110 ns" { clk add9910:inst3|Dout[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.110 ns" { clk clk~out0 add9910:inst3|Dout[0] } { 0.000ns 0.000ns 0.433ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "add9910.vhd" "" { Text "G:/vhdltext/fir/add9910.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "mult29.vhd" "" { Text "G:/vhdltext/fir/mult29.vhd" 36 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.208 ns" { add9910:inst3|Dout[0] mult29:inst27|Add3~224COUT1_226 mult29:inst27|Add3~221 mult29:inst27|Add4~244COUT1_252 mult29:inst27|Add4~242COUT1_253 mult29:inst27|Add4~239 mult29:inst27|Add1~370 mult29:inst27|Dout[6]~61 mult29:inst27|Dout[11]~56 mult29:inst27|Dout[12] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.208 ns" { add9910:inst3|Dout[0] mult29:inst27|Add3~224COUT1_226 mult29:inst27|Add3~221 mult29:inst27|Add4~244COUT1_252 mult29:inst27|Add4~242COUT1_253 mult29:inst27|Add4~239 mult29:inst27|Add1~370 mult29:inst27|Dout[6]~61 mult29:inst27|Dout[11]~56 mult29:inst27|Dout[12] } { 0.000ns 1.273ns 0.000ns 0.951ns 0.000ns 0.000ns 0.930ns 0.908ns 0.000ns 0.000ns } { 0.000ns 0.443ns 0.468ns 0.333ns 0.062ns 0.468ns 0.088ns 0.533ns 0.105ns 0.646ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.110 ns" { clk mult29:inst27|Dout[12] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.110 ns" { clk clk~out0 mult29:inst27|Dout[12] } { 0.000ns 0.000ns 0.433ns } { 0.000ns 1.130ns 0.547ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.110 ns" { clk add9910:inst3|Dout[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.110 ns" { clk clk~out0 add9910:inst3|Dout[0] } { 0.000ns 0.000ns 0.433ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "dff9:inst\|Dout\[3\] Din\[3\] clk 3.600 ns register " "Info: tsu for register \"dff9:inst\|Dout\[3\]\" (data pin = \"Din\[3\]\", clock pin = \"clk\") is 3.600 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.678 ns + Longest pin register " "Info: + Longest pin to register delay is 5.678 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns Din\[3\] 1 PIN PIN_91 1 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_91; Fanout = 1; PIN Node = 'Din\[3\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Din[3] } "NODE_NAME" } } { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 192 408 576 208 "Din\[8..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.454 ns) + CELL(0.089 ns) 5.678 ns dff9:inst\|Dout\[3\] 2 REG LC_X11_Y7_N9 1 " "Info: 2: + IC(4.454 ns) + CELL(0.089 ns) = 5.678 ns; Loc. = LC_X11_Y7_N9; Fanout = 1; REG Node = 'dff9:inst\|Dout\[3\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.543 ns" { Din[3] dff9:inst|Dout[3] } "NODE_NAME" } } { "dff9.vhd" "" { Text "G:/vhdltext/fir/dff9.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.224 ns ( 21.56 % ) " "Info: Total cell delay = 1.224 ns ( 21.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.454 ns ( 78.44 % ) " "Info: Total interconnect delay = 4.454 ns ( 78.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.678 ns" { Din[3] dff9:inst|Dout[3] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "5.678 ns" { Din[3] Din[3]~out0 dff9:inst|Dout[3] } { 0.000ns 0.000ns 4.454ns } { 0.000ns 1.135ns 0.089ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "dff9.vhd" "" { Text "G:/vhdltext/fir/dff9.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.107 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.107 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 329 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 329; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fir.bdf" "" { Schematic "G:/vhdltext/fir/fir.bdf" { { 128 408 576 144 "clk" "" } { 144 2056 2088 160 "clk" "" } { 152 2288 2320 168 "clk" "" } { 144 1616 1648 160 "clk" "" } { 144 1392 1424 160 "clk" "" } { 136 1144 1176 152 "clk" "" } { 136 936 960 152 "clk" "" } { 376 2280 2304 392 "clk" "" } { 376 2544 2568 392 "clk" "" } { 368 2000 2024 384 "clk" "" } { 360 1688 1712 376 "clk" "" } { 360 1440 1464 376 "clk" "" } { 360 1152 1176 376 "clk" "" } { 360 864 896 376 "clk" "" } { 360 608 640 376 "clk" "" } { 756 360 376 784 "clk" "" } { 752 696 712 784 "clk" "" } { 752 968 984 784 "clk" "" } { 744 1256 1272 776 "clk" "" } { 760 1792 1808 792 "clk" "" } { 752 2064 2080 784 "clk" "" } { 760 2320 2336 800 "clk" "" } { 1024 416 440 1040 "clk" "" } { 1016 1016 1032 1032 "clk" "" } { 744 1496 1512 784 "clk" "" } { 1032 1536 1552 1048 "clk" "" } { 1224 656 688 1240 "clk" "" } { 1192 1784 1808 1208 "clk" "" } { 1292 1336 1352 1320 "clk" "" } { 1032 2128 2152 1048 "clk" "" } { 616 904 928 632 "clk" "" } { 600 1168 1190 616 "clk" "" } { 600 1424 1456 616 "clk" "" } { 616 1728 1750 632 "clk" "" } { 616 1968 1992 632 "clk" "" } { 648 2240 2264 664 "clk" "" } { 616 2488 2520 632 "clk" "" } { 144 1840 1872 160 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.547 ns) 2.107 ns dff9:inst\|Dout\[3\] 2 REG LC_X11_Y7_N9 1 " "Info: 2: + IC(0.430 ns) + CELL(0.547 ns) = 2.107 ns; Loc. = LC_X11_Y7_N9; Fanout = 1; REG Node = 'dff9:inst\|Dout\[3\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.977 ns" { clk dff9:inst|Dout[3] } "NODE_NAME" } } { "dff9.vhd" "" { Text "G:/vhdltext/fir/dff9.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 79.59 % ) " "Info: Total cell delay = 1.677 ns ( 79.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.430 ns ( 20.41 % ) " "Info: Total interconnect delay = 0.430 ns ( 20.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.107 ns" { clk dff9:inst|Dout[3] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.107 ns" { clk clk~out0 dff9:inst|Dout[3] } { 0.000ns 0.000ns 0.430ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.678 ns" { Din[3] dff9:inst|Dout[3] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "5.678 ns" { Din[3] Din[3]~out0 dff9:inst|Dout[3] } { 0.000ns 0.000ns 4.454ns } { 0.000ns 1.135ns 0.089ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.107 ns" { clk dff9:inst|Dout[3] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.107 ns" { clk clk~out0 dff9:inst|Dout[3] } { 0.000ns 0.000ns 0.430ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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