fir.map.rpt

我自己用VHDL语言编的16阶FIR数字滤波器

    Info: Found entity 1: add121414
Info: Found 2 design units, including 1 entities, in source file add141415.vhd
    Info: Found design unit 1: add141415-a
    Info: Found entity 1: add141415
Warning: Can't analyze file -- file G:/vhdltext/fir/add141710.vhd is missing
Info: Found 2 design units, including 1 entities, in source file add151415.vhd
    Info: Found design unit 1: add151415-a
    Info: Found entity 1: add151415
Info: Found 2 design units, including 1 entities, in source file add161717.vhd
    Info: Found design unit 1: add161717-a
    Info: Found entity 1: add161717
Info: Found 2 design units, including 1 entities, in source file add9910.vhd
    Info: Found design unit 1: add9910-a
    Info: Found entity 1: add9910
Info: Found 2 design units, including 1 entities, in source file dff9.vhd
    Info: Found design unit 1: dff9-a
    Info: Found entity 1: dff9
Info: Found 2 design units, including 1 entities, in source file mult19.vhd
    Info: Found design unit 1: mult19-a
    Info: Found entity 1: mult19
Info: Found 2 design units, including 1 entities, in source file mult212.vhd
    Info: Found design unit 1: mult212-a
    Info: Found entity 1: mult212
Info: Found 2 design units, including 1 entities, in source file mult25.vhd
    Info: Found design unit 1: mult25-a
    Info: Found entity 1: mult25
Info: Found 2 design units, including 1 entities, in source file mult29.vhd
    Info: Found design unit 1: mult29-a
    Info: Found entity 1: mult29
Info: Found 2 design units, including 1 entities, in source file mult3.vhd
    Info: Found design unit 1: mult3-a
    Info: Found entity 1: mult3
Info: Found 2 design units, including 1 entities, in source file mult45.vhd
    Info: Found design unit 1: mult45-a
    Info: Found entity 1: mult45
Info: Found 2 design units, including 1 entities, in source file mult6.vhd
    Info: Found design unit 1: mult6-a
    Info: Found entity 1: mult6
Info: Found 2 design units, including 1 entities, in source file mult92.vhd
    Info: Found design unit 1: mult92-a
    Info: Found entity 1: mult92
Info: Found 2 design units, including 1 entities, in source file sub121414.vhd
    Info: Found design unit 1: sub121414-a
    Info: Found entity 1: sub121414
Info: Found 2 design units, including 1 entities, in source file sub171517.vhd
    Info: Found design unit 1: sub171517-a
    Info: Found entity 1: sub171517
Info: Found 1 design units, including 1 entities, in source file fir.bdf
    Info: Found entity 1: fir
Info: Elaborating entity "fir" for the top level hierarchy
Warning: Using design file add151710.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: add151710-a
    Info: Found entity 1: add151710
Info: Elaborating entity "add151710" for hierarchy "add151710:inst19"
Info: Elaborating entity "add141415" for hierarchy "add141415:inst37"
Info: Elaborating entity "add111414" for hierarchy "add111414:inst34"
Info: Elaborating entity "mult3" for hierarchy "mult3:inst28"
Warning (10492): VHDL Process Statement warning at mult3.vhd(20): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult3.vhd(23): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "add9910" for hierarchy "add9910:inst4"
Info: Elaborating entity "dff9" for hierarchy "dff9:inst6"
Info: Elaborating entity "mult29" for hierarchy "mult29:inst27"
Warning (10492): VHDL Process Statement warning at mult29.vhd(27): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult29.vhd(27): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult29.vhd(27): signal "s3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult29.vhd(30): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult29.vhd(30): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult29.vhd(30): signal "s3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "sub121414" for hierarchy "sub121414:inst32"
Info: Elaborating entity "mult19" for hierarchy "mult19:inst24"
Warning (10492): VHDL Process Statement warning at mult19.vhd(23): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult19.vhd(23): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult19.vhd(26): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult19.vhd(26): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "mult6" for hierarchy "mult6:inst30"
Warning (10492): VHDL Process Statement warning at mult6.vhd(23): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult6.vhd(23): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult6.vhd(26): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult6.vhd(26): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "sub171517" for hierarchy "sub171517:inst38"
Info: Elaborating entity "add151415" for hierarchy "add151415:inst35"
Info: Elaborating entity "mult25" for hierarchy "mult25:inst26"
Warning (10492): VHDL Process Statement warning at mult25.vhd(24): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult25.vhd(24): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult25.vhd(27): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult25.vhd(27): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "mult45" for hierarchy "mult45:inst29"
Warning (10492): VHDL Process Statement warning at mult45.vhd(27): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult45.vhd(27): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult45.vhd(27): signal "s3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult45.vhd(30): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult45.vhd(30): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult45.vhd(30): signal "s3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "add161717" for hierarchy "add161717:inst36"
Info: Elaborating entity "mult92" for hierarchy "mult92:inst31"
Warning (10492): VHDL Process Statement warning at mult92.vhd(31): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult92.vhd(31): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult92.vhd(31): signal "s3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult92.vhd(31): signal "s4" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult92.vhd(34): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult92.vhd(34): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult92.vhd(34): signal "s3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult92.vhd(34): signal "s4" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "mult212" for hierarchy "mult212:inst25"
Warning (10492): VHDL Process Statement warning at mult212.vhd(29): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult212.vhd(29): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult212.vhd(29): signal "s3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult212.vhd(29): signal "s4" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult212.vhd(32): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult212.vhd(32): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult212.vhd(32): signal "s3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult212.vhd(32): signal "s4" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: Reduced register "mult212:inst25|Dout[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "mult92:inst31|Dout[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "add161717:inst36|Dout[0]" with stuck data_in port to stuck value GND
Info: Implemented 615 device resources after synthesis - the final resource count might be different
    Info: Implemented 11 input pins
    Info: Implemented 10 output pins
    Info: Implemented 594 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 47 warnings
    Info: Processing ended: Sat May 03 12:06:42 2008
    Info: Elapsed time: 00:00:16