mult212.vhd

来自「我自己用VHDL语言编的16阶FIR数字滤波器」· VHDL 代码 · 共 42 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY mult212 is
PORT
( clk :  IN STD_LOGIC;
  Din :  IN SIGNED (9 DOWNTO 0);
 Dout :  OUT SIGNED (16 DOWNTO 0));
END mult212;

ARCHITECTURE a OF mult212 IS
SIGNAL s1 : SIGNED (16 DOWNTO 0);
SIGNAL s2 : SIGNED (15 DOWNTO 0);
SIGNAL s3 : SIGNED (13 DOWNTO 0);
SIGNAL s4 : SIGNED (11 DOWNTO 0);
SIGNAL s5 : SIGNED (16 DOWNTO 0);
BEGIN
P1:process(Din)
BEGIN
s1(16 DOWNTO 7)<=Din;
s1( 6 DOWNTO 0)<="0000000";
s2(15 DOWNTO 6)<=Din;
s2( 5 DOWNTO 0)<="000000";
s3(13 DOWNTO 4)<=Din;
s3( 3 DOWNTO 0)<="0000";
s4(11 DOWNTO 2)<=Din;
s4( 1 DOWNTO 0)<="00";
if Din(9)='0' then 
s5<=('0'&s1(16 downto 1))+("00"&s2(15 DOWNTO 1))+("0000"&s3(13 DOWNTO 1))+("000000"&s4(11 DOWNTO 1));

else 
s5<=('1'&s1(16 downto 1))+("11"&s2(15 DOWNTO 1))+("1111"&s3(13 DOWNTO 1))+("111111"&s4(11 DOWNTO 1));

end if;
end process;
P2: PROCESS(clk)
BEGIN
if clk'event and clk='1' then
Dout<=s5;
end if;
END PROCESS;
END a;