altlvds_ex3_msim.do

CPLD/FPGA常用模块与综合系统设计实例光盘程序

vlib work
vmap work work
vlib my_atom
vmap my_atom my_atom
vlib my_primitive
vmap my_primitive my_primitive
vlog -work work altlvds_s3_serial_link.vt altlvds_s3_serial_link.vo
vlog -work my_atom stratixiii_atoms.v
vlog -work my_primitive altera_primitives.v
vsim -L my_atom -L my_primitive -t ps work.altlvds_s3_serial_link_vlg_vec_tst
view wave
add wave -binary /altlvds_s3_serial_link_vlg_vec_tst/*test_rx_inclock
add wave -binary /altlvds_s3_serial_link_vlg_vec_tst/*test_rx_in
add wave -binary /altlvds_s3_serial_link_vlg_vec_tst/*test_rx_locked
add wave -binary /altlvds_s3_serial_link_vlg_vec_tst/*test_rx_out
add wave -binary /altlvds_s3_serial_link_vlg_vec_tst/*test_rx_divfwdclk
add wave -binary /altlvds_s3_serial_link_vlg_vec_tst/*test_rx_outclock
add wave -binary /altlvds_s3_serial_link_vlg_vec_tst/*recv_reg_clk
add wave -binary /altlvds_s3_serial_link_vlg_vec_tst/*parallel_core_data
add wave -binary /altlvds_s3_serial_link_vlg_vec_tst/*tran_reg_clk
add wave -binary /altlvds_s3_serial_link_vlg_vec_tst/*dataout_to_tran
add wave -binary /altlvds_s3_serial_link_vlg_vec_tst/*test_tx_inclock
add wave -binary /altlvds_s3_serial_link_vlg_vec_tst/*test_tx_locked
add wave -binary /altlvds_s3_serial_link_vlg_vec_tst/*test_tx_out
run 1us