altlvds_s3_serial_link.vo

CPLD/FPGA常用模块与综合系统设计实例光盘程序

	.clk(wire_rx_divfwdclk_0),
	.d(\rxreg[8]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(rxreg_8),
	.prn(vcc));
// synopsys translate_off
defparam \rxreg[8] .is_wysiwyg = "true";
defparam \rxreg[8] .power_up = "low";
// synopsys translate_on

// atom is at FF_X15_Y30_N19
dffeas \rxreg[9] (
	.clk(wire_rx_divfwdclk_0),
	.d(\rxreg[9]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(rxreg_9),
	.prn(vcc));
// synopsys translate_off
defparam \rxreg[9] .is_wysiwyg = "true";
defparam \rxreg[9] .power_up = "low";
// synopsys translate_on

// atom is at CLKCTRL_X0_Y30_N127
stratixiii_clkena \wire_rx_divfwdclk[0]~clkctrl (
	.inclk(wire_rx_divfwdclk[0]),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(wire_rx_divfwdclk_0),
	.enaout());
// synopsys translate_off
defparam \wire_rx_divfwdclk[0]~clkctrl .clock_type = "periphery clock";
defparam \wire_rx_divfwdclk[0]~clkctrl .ena_register_mode = "falling edge";
// synopsys translate_on

// atom is at SERDESRX_X0_Y30_N125
stratixiii_lvds_receiver rx_0(
	.datain(rx_in[0]),
	.clk0(wire_rx_clk0[0]),
	.enable0(wire_rx_enable0[0]),
	.dpareset(gnd),
	.dpahold(gnd),
	.dpaswitch(vcc),
	.fiforeset(gnd),
	.bitslip(gnd),
	.bitslipreset(gnd),
	.serialfbk(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.dpalock(),
	.bitslipmax(),
	.divfwdclk(wire_rx_divfwdclk[0]),
	.serialdataout(),
	.postdpaserialdataout(),
	.dpaclkout(),
	.dataout(rx_0_DATAOUT_bus));
// synopsys translate_off
defparam rx_0.align_to_rising_edge_only = "on";
defparam rx_0.channel_width = 10;
defparam rx_0.data_align_rollover = 10;
defparam rx_0.dpa_debug = "off";
defparam rx_0.dpa_output_clock_phase_shift = 0;
defparam rx_0.enable_dpa = "on";
defparam rx_0.enable_dpa_align_to_rising_edge_only = "off";
defparam rx_0.enable_soft_cdr = "on";
defparam rx_0.is_negative_ppm_drift = "off";
defparam rx_0.lose_lock_on_one_change = "off";
defparam rx_0.net_ppm_variation = 0;
defparam rx_0.reset_fifo_at_first_lock = "on";
defparam rx_0.rx_input_path_delay_engineering_bits = 0;
defparam rx_0.x_on_bitslip = "on";
// synopsys translate_on

// atom is at MLABCELL_X11_Y30_N28
stratixiii_lcell_comb \rx_soft_cdr_sync_reg[0]~feeder (
// Equation(s):
// \rx_soft_cdr_sync_reg[0]~feeder_combout  = wire_rx_dataout[0]

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(!wire_rx_dataout[0]),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\rx_soft_cdr_sync_reg[0]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \rx_soft_cdr_sync_reg[0]~feeder .extended_lut = "off";
defparam \rx_soft_cdr_sync_reg[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \rx_soft_cdr_sync_reg[0]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at FF_X11_Y30_N29
dffeas \rx_soft_cdr_sync_reg[0] (
	.clk(!wire_rx_divfwdclk_0),
	.d(\rx_soft_cdr_sync_reg[0]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(rx_soft_cdr_sync_reg[0]),
	.prn(vcc));
// synopsys translate_off
defparam \rx_soft_cdr_sync_reg[0] .is_wysiwyg = "true";
defparam \rx_soft_cdr_sync_reg[0] .power_up = "low";
// synopsys translate_on

// atom is at MLABCELL_X11_Y30_N30
stratixiii_lcell_comb \rxreg[0]~feeder (
// Equation(s):
// \rxreg[0]~feeder_combout  = rx_soft_cdr_sync_reg[0]

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(!rx_soft_cdr_sync_reg[0]),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\rxreg[0]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \rxreg[0]~feeder .extended_lut = "off";
defparam \rxreg[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \rxreg[0]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at MLABCELL_X19_Y27_N10
stratixiii_lcell_comb \rx_soft_cdr_sync_reg[1]~feeder (
// Equation(s):
// \rx_soft_cdr_sync_reg[1]~feeder_combout  = wire_rx_dataout[1]

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(!wire_rx_dataout[1]),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\rx_soft_cdr_sync_reg[1]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \rx_soft_cdr_sync_reg[1]~feeder .extended_lut = "off";
defparam \rx_soft_cdr_sync_reg[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \rx_soft_cdr_sync_reg[1]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at FF_X19_Y27_N11
dffeas \rx_soft_cdr_sync_reg[1] (
	.clk(!wire_rx_divfwdclk_0),
	.d(\rx_soft_cdr_sync_reg[1]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(rx_soft_cdr_sync_reg[1]),
	.prn(vcc));
// synopsys translate_off
defparam \rx_soft_cdr_sync_reg[1] .is_wysiwyg = "true";
defparam \rx_soft_cdr_sync_reg[1] .power_up = "low";
// synopsys translate_on

// atom is at MLABCELL_X19_Y27_N8
stratixiii_lcell_comb \rxreg[1]~feeder (
// Equation(s):
// \rxreg[1]~feeder_combout  = rx_soft_cdr_sync_reg[1]

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(!rx_soft_cdr_sync_reg[1]),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\rxreg[1]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \rxreg[1]~feeder .extended_lut = "off";
defparam \rxreg[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \rxreg[1]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at MLABCELL_X21_Y30_N32
stratixiii_lcell_comb \rx_soft_cdr_sync_reg[2]~feeder (
// Equation(s):
// \rx_soft_cdr_sync_reg[2]~feeder_combout  = wire_rx_dataout[2]

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(!wire_rx_dataout[2]),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\rx_soft_cdr_sync_reg[2]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \rx_soft_cdr_sync_reg[2]~feeder .extended_lut = "off";
defparam \rx_soft_cdr_sync_reg[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \rx_soft_cdr_sync_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at FF_X21_Y30_N33
dffeas \rx_soft_cdr_sync_reg[2] (
	.clk(!wire_rx_divfwdclk_0),
	.d(\rx_soft_cdr_sync_reg[2]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(rx_soft_cdr_sync_reg[2]),
	.prn(vcc));
// synopsys translate_off
defparam \rx_soft_cdr_sync_reg[2] .is_wysiwyg = "true";
defparam \rx_soft_cdr_sync_reg[2] .power_up = "low";
// synopsys translate_on

// atom is at MLABCELL_X21_Y30_N34
stratixiii_lcell_comb \rxreg[2]~feeder (
// Equation(s):
// \rxreg[2]~feeder_combout  = rx_soft_cdr_sync_reg[2]

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(!rx_soft_cdr_sync_reg[2]),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\rxreg[2]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \rxreg[2]~feeder .extended_lut = "off";
defparam \rxreg[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \rxreg[2]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at LABCELL_X2_Y30_N2
stratixiii_lcell_comb \rx_soft_cdr_sync_reg[3]~feeder (
// Equation(s):
// \rx_soft_cdr_sync_reg[3]~feeder_combout  = wire_rx_dataout[3]

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(!wire_rx_dataout[3]),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\rx_soft_cdr_sync_reg[3]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \rx_soft_cdr_sync_reg[3]~feeder .extended_lut = "off";
defparam \rx_soft_cdr_sync_reg[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \rx_soft_cdr_sync_reg[3]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at FF_X2_Y30_N3
dffeas \rx_soft_cdr_sync_reg[3] (
	.clk(!wire_rx_divfwdclk_0),
	.d(\rx_soft_cdr_sync_reg[3]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(rx_soft_cdr_sync_reg[3]),
	.prn(vcc));
// synopsys translate_off
defparam \rx_soft_cdr_sync_reg[3] .is_wysiwyg = "true";
defparam \rx_soft_cdr_sync_reg[3] .power_up = "low";
// synopsys translate_on

// atom is at LABCELL_X2_Y30_N0
stratixiii_lcell_comb \rxreg[3]~feeder (
// Equation(s):
// \rxreg[3]~feeder_combout  = rx_soft_cdr_sync_reg[3]

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(!rx_soft_cdr_sync_reg[3]),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\rxreg[3]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \rxreg[3]~feeder .extended_lut = "off";
defparam \rxreg[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \rxreg[3]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at LABCELL_X14_Y31_N20
stratixiii_lcell_comb \rx_soft_cdr_sync_reg[4]~feeder (
// Equation(s):
// \rx_soft_cdr_sync_reg[4]~feeder_combout  = wire_rx_dataout[4]

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(!wire_rx_dataout[4]),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\rx_soft_cdr_sync_reg[4]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \rx_soft_cdr_sync_reg[4]~feeder .extended_lut = "off";
defparam \rx_soft_cdr_sync_reg[4]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \rx_soft_cdr_sync_reg[4]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at FF_X14_Y31_N21
dffeas \rx_soft_cdr_sync_reg[4] (
	.clk(!wire_rx_divfwdclk_0),
	.d(\rx_soft_cdr_sync_reg[4]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(rx_soft_cdr_sync_reg[4]),
	.prn(vcc));
// synopsys translate_off
defparam \rx_soft_cdr_sync_reg[4] .is_wysiwyg = "true";
defparam \rx_soft_cdr_sync_reg[4] .power_up = "low";
// synopsys translate_on

// atom is at MLABCELL_X15_Y31_N30
stratixiii_lcell_comb \rxreg[4]~feeder (
// Equation(s):
// \rxreg[4]~feeder_combout  = rx_soft_cdr_sync_reg[4]

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(!rx_soft_cdr_sync_reg[4]),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\rxreg[4]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \rxreg[4]~feeder .extended_lut = "off";
defparam \rxreg[4]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \rxreg[4]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at MLABCELL_X1_Y30_N2
stratixiii_lcell_comb \rx_soft_cdr_sync_reg[5]~feeder (
// Equation(s):
// \rx_soft_cdr_sync_reg[5]~feeder_combout  = wire_rx_dataout[5]

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(!wire_rx_dataout[5]),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\rx_soft_cdr_sync_reg[5]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \rx_soft_cdr_sync_reg[5]~feeder .extended_lut = "off";
defparam \rx_soft_cdr_sync_reg[5]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \rx_soft_cdr_sync_reg[5]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at FF_X1_Y30_N3
dffeas \rx_soft_cdr_sync_reg[5] (
	.clk(!wire_rx_divfwdclk_0),
	.d(\rx_soft_cdr_sync_reg[5]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(rx_soft_cdr_sync_reg[5]),
	.prn(vcc));
// synopsys translate_off
defparam \rx_soft_cdr_sync_reg[5] .is_wysiwyg = "true";
defparam \rx_soft_cdr_sync_reg[5] .power_up = "low";
// synopsys translate_on

// atom is at MLABCELL_X1_Y30_N0
stratixiii_lcell_comb \rxreg