altlvds_s3_serial_link.vo

CPLD/FPGA常用模块与综合系统设计实例光盘程序

output 	rx_locked;
output 	rx_outclock;
output 	rxreg_0;
output 	rxreg_1;
output 	rxreg_2;
output 	rxreg_3;
output 	rxreg_4;
output 	rxreg_5;
output 	rxreg_6;
output 	rxreg_7;
output 	rxreg_8;
output 	rxreg_9;
input 	[0:0] rx_in;
input 	rx_inclock;
output 	wire_rx_divfwdclk_0;
input 	devpor;
input 	devclrn;
input 	devoe;

wire gnd = 1'b0;
wire vcc = 1'b1;



rx_block_lvds_rx auto_generated(
	.rx_locked(rx_locked),
	.rx_outclock(rx_outclock),
	.rxreg_0(rxreg_0),
	.rxreg_1(rxreg_1),
	.rxreg_2(rxreg_2),
	.rxreg_3(rxreg_3),
	.rxreg_4(rxreg_4),
	.rxreg_5(rxreg_5),
	.rxreg_6(rxreg_6),
	.rxreg_7(rxreg_7),
	.rxreg_8(rxreg_8),
	.rxreg_9(rxreg_9),
	.rx_in({rx_in[0]}),
	.rx_inclock(rx_inclock),
	.wire_rx_divfwdclk_0(wire_rx_divfwdclk_0),
	.devpor(devpor),
	.devclrn(devclrn),
	.devoe(devoe));

endmodule

module rx_block_lvds_rx (
	rx_locked,
	rx_outclock,
	rxreg_0,
	rxreg_1,
	rxreg_2,
	rxreg_3,
	rxreg_4,
	rxreg_5,
	rxreg_6,
	rxreg_7,
	rxreg_8,
	rxreg_9,
	rx_in,
	rx_inclock,
	wire_rx_divfwdclk_0,
	devpor,
	devclrn,
	devoe);
output 	rx_locked;
output 	rx_outclock;
output 	rxreg_0;
output 	rxreg_1;
output 	rxreg_2;
output 	rxreg_3;
output 	rxreg_4;
output 	rxreg_5;
output 	rxreg_6;
output 	rxreg_7;
output 	rxreg_8;
output 	rxreg_9;
input 	[0:0] rx_in;
input 	rx_inclock;
output 	wire_rx_divfwdclk_0;
input 	devpor;
input 	devclrn;
input 	devoe;

wire gnd = 1'b0;
wire vcc = 1'b1;

wire wire_pll_fbout;
wire \rx_soft_cdr_sync_reg[0]~feeder_combout ;
wire \rxreg[0]~feeder_combout ;
wire \rx_soft_cdr_sync_reg[1]~feeder_combout ;
wire \rxreg[1]~feeder_combout ;
wire \rx_soft_cdr_sync_reg[2]~feeder_combout ;
wire \rxreg[2]~feeder_combout ;
wire \rx_soft_cdr_sync_reg[3]~feeder_combout ;
wire \rxreg[3]~feeder_combout ;
wire \rx_soft_cdr_sync_reg[4]~feeder_combout ;
wire \rxreg[4]~feeder_combout ;
wire \rx_soft_cdr_sync_reg[5]~feeder_combout ;
wire \rxreg[5]~feeder_combout ;
wire \rx_soft_cdr_sync_reg[6]~feeder_combout ;
wire \rxreg[6]~feeder_combout ;
wire \rx_soft_cdr_sync_reg[7]~feeder_combout ;
wire \rxreg[7]~feeder_combout ;
wire \rx_soft_cdr_sync_reg[8]~feeder_combout ;
wire \rxreg[8]~feeder_combout ;
wire \rx_soft_cdr_sync_reg[9]~feeder_combout ;
wire \rxreg[9]~feeder_combout ;
wire [9:0] rx_soft_cdr_sync_reg;
wire [9:0] wire_pll_clk;
wire [0:0] wire_rx_clk0;
wire [9:0] wire_rx_dataout;
wire [0:0] wire_rx_divfwdclk;
wire [0:0] wire_rx_enable0;

wire [9:0] rx_0_DATAOUT_bus;
wire [9:0] pll_CLK_bus;

assign wire_rx_dataout[0] = rx_0_DATAOUT_bus[0];
assign wire_rx_dataout[1] = rx_0_DATAOUT_bus[1];
assign wire_rx_dataout[2] = rx_0_DATAOUT_bus[2];
assign wire_rx_dataout[3] = rx_0_DATAOUT_bus[3];
assign wire_rx_dataout[4] = rx_0_DATAOUT_bus[4];
assign wire_rx_dataout[5] = rx_0_DATAOUT_bus[5];
assign wire_rx_dataout[6] = rx_0_DATAOUT_bus[6];
assign wire_rx_dataout[7] = rx_0_DATAOUT_bus[7];
assign wire_rx_dataout[8] = rx_0_DATAOUT_bus[8];
assign wire_rx_dataout[9] = rx_0_DATAOUT_bus[9];

assign wire_rx_clk0[0] = pll_CLK_bus[0];
assign wire_rx_enable0[0] = pll_CLK_bus[1];
assign wire_pll_clk[2] = pll_CLK_bus[2];
assign wire_pll_clk[3] = pll_CLK_bus[3];
assign wire_pll_clk[4] = pll_CLK_bus[4];
assign wire_pll_clk[5] = pll_CLK_bus[5];
assign wire_pll_clk[6] = pll_CLK_bus[6];
assign wire_pll_clk[7] = pll_CLK_bus[7];
assign wire_pll_clk[8] = pll_CLK_bus[8];
assign wire_pll_clk[9] = pll_CLK_bus[9];

rx_block_altclkctrl rx_outclock_buf(
	.inclk({gnd,gnd,gnd,wire_pll_clk[2]}),
	.outclk(rx_outclock),
	.devpor(devpor),
	.devclrn(devclrn),
	.devoe(devoe));

// atom is at PLL_L2
stratixiii_pll pll(
	.areset(gnd),
	.pfdena(vcc),
	.fbin(wire_pll_fbout),
	.phaseupdown(gnd),
	.phasestep(gnd),
	.scandata(gnd),
	.scanclk(gnd),
	.scanclkena(vcc),
	.configupdate(gnd),
	.clkswitch(gnd),
	.inclk({gnd,rx_inclock}),
	.phasecounterselect(4'b0000),
	.phasedone(),
	.scandataout(),
	.scandone(),
	.activeclock(),
	.locked(rx_locked),
	.vcooverrange(),
	.vcounderrange(),
	.fbout(wire_pll_fbout),
	.clk(pll_CLK_bus),
	.clkbad());
// synopsys translate_off
defparam pll.bandwidth_type = "auto";
defparam pll.c0_high = 5;
defparam pll.c0_initial = 1;
defparam pll.c0_low = 5;
defparam pll.c0_mode = "even";
defparam pll.c0_ph = 0;
defparam pll.c1_high = 0;
defparam pll.c1_initial = 0;
defparam pll.c1_low = 0;
defparam pll.c1_mode = "bypass";
defparam pll.c1_ph = 0;
defparam pll.c1_use_casc_in = "off";
defparam pll.c2_high = 0;
defparam pll.c2_initial = 0;
defparam pll.c2_low = 0;
defparam pll.c2_mode = "bypass";
defparam pll.c2_ph = 0;
defparam pll.c2_use_casc_in = "off";
defparam pll.c3_high = 1;
defparam pll.c3_initial = 1;
defparam pll.c3_low = 0;
defparam pll.c3_mode = "bypass";
defparam pll.c3_ph = 0;
defparam pll.c3_use_casc_in = "off";
defparam pll.c4_high = 0;
defparam pll.c4_initial = 0;
defparam pll.c4_low = 0;
defparam pll.c4_mode = "bypass";
defparam pll.c4_ph = 0;
defparam pll.c4_use_casc_in = "off";
defparam pll.c5_high = 1;
defparam pll.c5_initial = 9;
defparam pll.c5_low = 9;
defparam pll.c5_mode = "even";
defparam pll.c5_ph = 4;
defparam pll.c5_use_casc_in = "off";
defparam pll.c6_high = 0;
defparam pll.c6_initial = 0;
defparam pll.c6_low = 0;
defparam pll.c6_mode = "bypass";
defparam pll.c6_ph = 0;
defparam pll.c6_use_casc_in = "off";
defparam pll.c7_high = 0;
defparam pll.c7_initial = 0;
defparam pll.c7_low = 0;
defparam pll.c7_mode = "bypass";
defparam pll.c7_ph = 0;
defparam pll.c7_use_casc_in = "off";
defparam pll.c8_high = 0;
defparam pll.c8_initial = 0;
defparam pll.c8_low = 0;
defparam pll.c8_mode = "bypass";
defparam pll.c8_ph = 0;
defparam pll.c8_use_casc_in = "off";
defparam pll.c9_high = 0;
defparam pll.c9_initial = 0;
defparam pll.c9_low = 0;
defparam pll.c9_mode = "bypass";
defparam pll.c9_ph = 0;
defparam pll.c9_use_casc_in = "off";
defparam pll.charge_pump_current_bits = 1;
defparam pll.clk0_counter = "c3";
defparam pll.clk0_divide_by = 1;
defparam pll.clk0_duty_cycle = 50;
defparam pll.clk0_multiply_by = 20;
defparam pll.clk0_phase_shift = "-500";
defparam pll.clk1_counter = "c5";
defparam pll.clk1_divide_by = 1;
defparam pll.clk1_duty_cycle = 10;
defparam pll.clk1_multiply_by = 2;
defparam pll.clk1_phase_shift = "8000";
defparam pll.clk2_counter = "c0";
defparam pll.clk2_divide_by = 1;
defparam pll.clk2_duty_cycle = 50;
defparam pll.clk2_multiply_by = 2;
defparam pll.clk2_phase_shift = "-500";
defparam pll.clk3_counter = "unused";
defparam pll.clk3_divide_by = 0;
defparam pll.clk3_duty_cycle = 50;
defparam pll.clk3_multiply_by = 0;
defparam pll.clk3_phase_shift = "0";
defparam pll.clk4_counter = "unused";
defparam pll.clk4_divide_by = 0;
defparam pll.clk4_duty_cycle = 50;
defparam pll.clk4_multiply_by = 0;
defparam pll.clk4_phase_shift = "0";
defparam pll.clk5_counter = "unused";
defparam pll.clk5_divide_by = 0;
defparam pll.clk5_duty_cycle = 50;
defparam pll.clk5_multiply_by = 0;
defparam pll.clk5_phase_shift = "0";
defparam pll.clk6_counter = "unused";
defparam pll.clk6_divide_by = 0;
defparam pll.clk6_duty_cycle = 50;
defparam pll.clk6_multiply_by = 0;
defparam pll.clk6_phase_shift = "0";
defparam pll.clk7_counter = "unused";
defparam pll.clk7_divide_by = 0;
defparam pll.clk7_duty_cycle = 50;
defparam pll.clk7_multiply_by = 0;
defparam pll.clk7_phase_shift = "0";
defparam pll.clk8_counter = "unused";
defparam pll.clk8_divide_by = 0;
defparam pll.clk8_duty_cycle = 50;
defparam pll.clk8_multiply_by = 0;
defparam pll.clk8_phase_shift = "0";
defparam pll.clk9_counter = "unused";
defparam pll.clk9_divide_by = 0;
defparam pll.clk9_duty_cycle = 50;
defparam pll.clk9_multiply_by = 0;
defparam pll.clk9_phase_shift = "0";
defparam pll.compensate_clock = "lvds clock";
defparam pll.dpa_divide_by = 1;
defparam pll.dpa_divider = 1;
defparam pll.dpa_multiply_by = 20;
defparam pll.inclk0_input_frequency = 20000;
defparam pll.inclk1_input_frequency = 0;
defparam pll.lock_c = 0;
defparam pll.loop_filter_c_bits = 0;
defparam pll.loop_filter_r_bits = 27;
defparam pll.m = 20;
defparam pll.m_initial = 1;
defparam pll.m_ph = 4;
defparam pll.n = 1;
defparam pll.operation_mode = "source synchronous";
defparam pll.pfd_max = 200000;
defparam pll.pfd_min = 3076;
defparam pll.pll_compensation_delay = 2041;
defparam pll.pll_type = "fast";
defparam pll.self_reset_on_loss_lock = "off";
defparam pll.simulation_type = "functional";
defparam pll.switch_over_type = "auto";
defparam pll.vco_center = 769;
defparam pll.vco_divide_by = 0;
defparam pll.vco_frequency_control = "auto";
defparam pll.vco_max = 1666;
defparam pll.vco_min = 769;
defparam pll.vco_multiply_by = 0;
defparam pll.vco_phase_shift_step = 125;
defparam pll.vco_post_scale = 1;
// synopsys translate_on

// atom is at FF_X11_Y30_N31
dffeas \rxreg[0] (
	.clk(wire_rx_divfwdclk_0),
	.d(\rxreg[0]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(rxreg_0),
	.prn(vcc));
// synopsys translate_off
defparam \rxreg[0] .is_wysiwyg = "true";
defparam \rxreg[0] .power_up = "low";
// synopsys translate_on

// atom is at FF_X19_Y27_N9
dffeas \rxreg[1] (
	.clk(wire_rx_divfwdclk_0),
	.d(\rxreg[1]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(rxreg_1),
	.prn(vcc));
// synopsys translate_off
defparam \rxreg[1] .is_wysiwyg = "true";
defparam \rxreg[1] .power_up = "low";
// synopsys translate_on

// atom is at FF_X21_Y30_N35
dffeas \rxreg[2] (
	.clk(wire_rx_divfwdclk_0),
	.d(\rxreg[2]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(rxreg_2),
	.prn(vcc));
// synopsys translate_off
defparam \rxreg[2] .is_wysiwyg = "true";
defparam \rxreg[2] .power_up = "low";
// synopsys translate_on

// atom is at FF_X2_Y30_N1
dffeas \rxreg[3] (
	.clk(wire_rx_divfwdclk_0),
	.d(\rxreg[3]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(rxreg_3),
	.prn(vcc));
// synopsys translate_off
defparam \rxreg[3] .is_wysiwyg = "true";
defparam \rxreg[3] .power_up = "low";
// synopsys translate_on

// atom is at FF_X15_Y31_N31
dffeas \rxreg[4] (
	.clk(wire_rx_divfwdclk_0),
	.d(\rxreg[4]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(rxreg_4),
	.prn(vcc));
// synopsys translate_off
defparam \rxreg[4] .is_wysiwyg = "true";
defparam \rxreg[4] .power_up = "low";
// synopsys translate_on

// atom is at FF_X1_Y30_N1
dffeas \rxreg[5] (
	.clk(wire_rx_divfwdclk_0),
	.d(\rxreg[5]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(rxreg_5),
	.prn(vcc));
// synopsys translate_off
defparam \rxreg[5] .is_wysiwyg = "true";
defparam \rxreg[5] .power_up = "low";
// synopsys translate_on

// atom is at FF_X8_Y30_N1
dffeas \rxreg[6] (
	.clk(wire_rx_divfwdclk_0),
	.d(\rxreg[6]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(rxreg_6),
	.prn(vcc));
// synopsys translate_off
defparam \rxreg[6] .is_wysiwyg = "true";
defparam \rxreg[6] .power_up = "low";
// synopsys translate_on

// atom is at FF_X12_Y30_N1
dffeas \rxreg[7] (
	.clk(wire_rx_divfwdclk_0),
	.d(\rxreg[7]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(rxreg_7),
	.prn(vcc));
// synopsys translate_off
defparam \rxreg[7] .is_wysiwyg = "true";
defparam \rxreg[7] .power_up = "low";
// synopsys translate_on

// atom is at FF_X4_Y30_N7
dffeas \rxreg[8] (