altlvds_s3_serial_link.vo

CPLD/FPGA常用模块与综合系统设计实例光盘程序

output 	dffs_3;
output 	dffs_4;
output 	dffs_5;
output 	dffs_6;
output 	dffs_7;
output 	dffs_8;
output 	dffs_9;
input 	clock;
input 	devpor;
input 	devclrn;
input 	devoe;

wire gnd = 1'b0;
wire vcc = 1'b1;

wire \dffs[0]~feeder_combout ;
wire \dffs[1]~feeder_combout ;
wire \dffs[3]~feeder_combout ;
wire \dffs[6]~feeder_combout ;
wire \dffs[7]~feeder_combout ;
wire \dffs[8]~feeder_combout ;
wire \dffs[9]~feeder_combout ;


// atom is at FF_X90_Y27_N33
dffeas \dffs[0] (
	.clk(clock),
	.d(\dffs[0]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(dffs_0),
	.prn(vcc));
// synopsys translate_off
defparam \dffs[0] .is_wysiwyg = "true";
defparam \dffs[0] .power_up = "low";
// synopsys translate_on

// atom is at FF_X86_Y27_N17
dffeas \dffs[1] (
	.clk(clock),
	.d(\dffs[1]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(dffs_1),
	.prn(vcc));
// synopsys translate_off
defparam \dffs[1] .is_wysiwyg = "true";
defparam \dffs[1] .power_up = "low";
// synopsys translate_on

// atom is at FF_X87_Y35_N37
dffeas \dffs[2] (
	.clk(clock),
	.d(gnd),
	.asdata(rxreg_2),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(dffs_2),
	.prn(vcc));
// synopsys translate_off
defparam \dffs[2] .is_wysiwyg = "true";
defparam \dffs[2] .power_up = "low";
// synopsys translate_on

// atom is at FF_X90_Y35_N33
dffeas \dffs[3] (
	.clk(clock),
	.d(\dffs[3]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(dffs_3),
	.prn(vcc));
// synopsys translate_off
defparam \dffs[3] .is_wysiwyg = "true";
defparam \dffs[3] .power_up = "low";
// synopsys translate_on

// atom is at FF_X15_Y31_N29
dffeas \dffs[4] (
	.clk(clock),
	.d(gnd),
	.asdata(rxreg_4),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(dffs_4),
	.prn(vcc));
// synopsys translate_off
defparam \dffs[4] .is_wysiwyg = "true";
defparam \dffs[4] .power_up = "low";
// synopsys translate_on

// atom is at FF_X17_Y31_N3
dffeas \dffs[5] (
	.clk(clock),
	.d(gnd),
	.asdata(rxreg_5),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(dffs_5),
	.prn(vcc));
// synopsys translate_off
defparam \dffs[5] .is_wysiwyg = "true";
defparam \dffs[5] .power_up = "low";
// synopsys translate_on

// atom is at FF_X89_Y30_N33
dffeas \dffs[6] (
	.clk(clock),
	.d(\dffs[6]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(dffs_6),
	.prn(vcc));
// synopsys translate_off
defparam \dffs[6] .is_wysiwyg = "true";
defparam \dffs[6] .power_up = "low";
// synopsys translate_on

// atom is at FF_X90_Y30_N39
dffeas \dffs[7] (
	.clk(clock),
	.d(\dffs[7]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(dffs_7),
	.prn(vcc));
// synopsys translate_off
defparam \dffs[7] .is_wysiwyg = "true";
defparam \dffs[7] .power_up = "low";
// synopsys translate_on

// atom is at FF_X87_Y30_N11
dffeas \dffs[8] (
	.clk(clock),
	.d(\dffs[8]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(dffs_8),
	.prn(vcc));
// synopsys translate_off
defparam \dffs[8] .is_wysiwyg = "true";
defparam \dffs[8] .power_up = "low";
// synopsys translate_on

// atom is at FF_X89_Y27_N33
dffeas \dffs[9] (
	.clk(clock),
	.d(\dffs[9]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(dffs_9),
	.prn(vcc));
// synopsys translate_off
defparam \dffs[9] .is_wysiwyg = "true";
defparam \dffs[9] .power_up = "low";
// synopsys translate_on

// atom is at LABCELL_X90_Y27_N32
stratixiii_lcell_comb \dffs[0]~feeder (
// Equation(s):
// \dffs[0]~feeder_combout  = rxreg_0

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(!rxreg_0),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\dffs[0]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \dffs[0]~feeder .extended_lut = "off";
defparam \dffs[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \dffs[0]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at MLABCELL_X86_Y27_N16
stratixiii_lcell_comb \dffs[1]~feeder (
// Equation(s):
// \dffs[1]~feeder_combout  = rxreg_1

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(!rxreg_1),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\dffs[1]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \dffs[1]~feeder .extended_lut = "off";
defparam \dffs[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \dffs[1]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at LABCELL_X90_Y35_N32
stratixiii_lcell_comb \dffs[3]~feeder (
// Equation(s):
// \dffs[3]~feeder_combout  = rxreg_3

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(!rxreg_3),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\dffs[3]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \dffs[3]~feeder .extended_lut = "off";
defparam \dffs[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \dffs[3]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at MLABCELL_X89_Y30_N32
stratixiii_lcell_comb \dffs[6]~feeder (
// Equation(s):
// \dffs[6]~feeder_combout  = rxreg_6

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(!rxreg_6),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\dffs[6]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \dffs[6]~feeder .extended_lut = "off";
defparam \dffs[6]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \dffs[6]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at LABCELL_X90_Y30_N38
stratixiii_lcell_comb \dffs[7]~feeder (
// Equation(s):
// \dffs[7]~feeder_combout  = rxreg_7

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(!rxreg_7),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\dffs[7]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \dffs[7]~feeder .extended_lut = "off";
defparam \dffs[7]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \dffs[7]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at LABCELL_X87_Y30_N10
stratixiii_lcell_comb \dffs[8]~feeder (
// Equation(s):
// \dffs[8]~feeder_combout  = rxreg_8

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(!rxreg_8),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\dffs[8]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \dffs[8]~feeder .extended_lut = "off";
defparam \dffs[8]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \dffs[8]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at MLABCELL_X89_Y27_N32
stratixiii_lcell_comb \dffs[9]~feeder (
// Equation(s):
// \dffs[9]~feeder_combout  = rxreg_9

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(!rxreg_9),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\dffs[9]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \dffs[9]~feeder .extended_lut = "off";
defparam \dffs[9]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \dffs[9]~feeder .shared_arith = "off";
// synopsys translate_on

endmodule

module rx_block (
	rx_locked,
	rx_outclock,
	rxreg_0,
	rxreg_1,
	rxreg_2,
	rxreg_3,
	rxreg_4,
	rxreg_5,
	rxreg_6,
	rxreg_7,
	rxreg_8,
	rxreg_9,
	test_rx_in,
	test_rx_inclock,
	wire_rx_divfwdclk_0,
	devpor,
	devclrn,
	devoe);
output 	rx_locked;
output 	rx_outclock;
output 	rxreg_0;
output 	rxreg_1;
output 	rxreg_2;
output 	rxreg_3;
output 	rxreg_4;
output 	rxreg_5;
output 	rxreg_6;
output 	rxreg_7;
output 	rxreg_8;
output 	rxreg_9;
input 	test_rx_in;
input 	test_rx_inclock;
output 	wire_rx_divfwdclk_0;
input 	devpor;
input 	devclrn;
input 	devoe;

wire gnd = 1'b0;
wire vcc = 1'b1;



altlvds_rx altlvds_rx_component(
	.rx_locked(rx_locked),
	.rx_outclock(rx_outclock),
	.rxreg_0(rxreg_0),
	.rxreg_1(rxreg_1),
	.rxreg_2(rxreg_2),
	.rxreg_3(rxreg_3),
	.rxreg_4(rxreg_4),
	.rxreg_5(rxreg_5),
	.rxreg_6(rxreg_6),
	.rxreg_7(rxreg_7),
	.rxreg_8(rxreg_8),
	.rxreg_9(rxreg_9),
	.rx_in({test_rx_in}),
	.rx_inclock(test_rx_inclock),
	.wire_rx_divfwdclk_0(wire_rx_divfwdclk_0),
	.devpor(devpor),
	.devclrn(devclrn),
	.devoe(devoe));

endmodule

module altlvds_rx (
	rx_locked,
	rx_outclock,
	rxreg_0,
	rxreg_1,
	rxreg_2,
	rxreg_3,
	rxreg_4,
	rxreg_5,
	rxreg_6,
	rxreg_7,
	rxreg_8,
	rxreg_9,
	rx_in,
	rx_inclock,
	wire_rx_divfwdclk_0,
	devpor,
	devclrn,
	devoe);