altlvds_s3_serial_link.vo

CPLD/FPGA常用模块与综合系统设计实例光盘程序

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 7.2 Build 147 09/05/2007 SJ Full Version"

// DATE "09/10/2007 15:43:38"

// 
// Device: Altera EP3SL150F780C2 Package FBGA780
// 

// 
// This Verilog file should be used for ModelSim-Altera (Verilog) only
// 

`timescale 1 ps/ 1 ps

module altlvds_s3_serial_link (
	\test_tx_out(n) ,
	\test_rx_in(n) ,
	\test_rx_inclock(n) ,
	test_tx_inclock,
	test_tx_locked,
	test_rx_inclock,
	test_rx_divfwdclk,
	test_rx_locked,
	test_rx_out,
	test_tx_out,
	test_rx_in,
	test_rx_outclock,
	parallel_core_data,
	dataout_to_tran,
	recv_reg_clk,
	tran_reg_clk);
output 	\test_tx_out(n) ;
input 	\test_rx_in(n) ;
input 	\test_rx_inclock(n) ;
input 	test_tx_inclock;
output 	test_tx_locked;
input 	test_rx_inclock;
output 	test_rx_divfwdclk;
output 	test_rx_locked;
output 	[9:0] test_rx_out;
output 	test_tx_out;
input 	test_rx_in;
output 	test_rx_outclock;
output 	[9:0] parallel_core_data;
output 	[9:0] dataout_to_tran;
input 	recv_reg_clk;
input 	tran_reg_clk;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \u1|altlvds_tx_component|auto_generated|wire_pll_locked ;
wire \u2|altlvds_rx_component|auto_generated|wire_pll_locked ;
wire \u2|altlvds_rx_component|auto_generated|rx_outclock_buf|wire_clkctrl3_outclk ;
wire \test_tx_inclock~input_o ;
wire \test_rx_in~input_o ;
wire \test_rx_inclock~input_o ;
wire \recv_reg_clk~input_o ;
wire \tran_reg_clk~input_o ;
wire \u2|altlvds_rx_component|auto_generated|wire_rx_divfwdclk[0]~clkctrl_outclk ;
wire \recv_reg_clk~inputclkctrl_outclk ;
wire \tran_reg_clk~inputclkctrl_outclk ;
wire [9:0] \u7|lpm_ff_component|dffs ;
wire [9:0] \u2|altlvds_rx_component|auto_generated|rxreg ;
wire [0:0] \u1|altlvds_tx_component|auto_generated|wire_tx_dataout ;
wire [9:0] \u8|lpm_ff_component|dffs ;


tx_block u1(
	.tx_locked(\u1|altlvds_tx_component|auto_generated|wire_pll_locked ),
	.wire_tx_dataout_0(\u1|altlvds_tx_component|auto_generated|wire_tx_dataout [0]),
	.dffs_0(\u8|lpm_ff_component|dffs [0]),
	.dffs_1(\u8|lpm_ff_component|dffs [1]),
	.dffs_2(\u8|lpm_ff_component|dffs [2]),
	.dffs_3(\u8|lpm_ff_component|dffs [3]),
	.dffs_4(\u8|lpm_ff_component|dffs [4]),
	.dffs_5(\u8|lpm_ff_component|dffs [5]),
	.dffs_6(\u8|lpm_ff_component|dffs [6]),
	.dffs_7(\u8|lpm_ff_component|dffs [7]),
	.dffs_8(\u8|lpm_ff_component|dffs [8]),
	.dffs_9(\u8|lpm_ff_component|dffs [9]),
	.test_tx_inclock(\test_tx_inclock~input_o ),
	.devpor(devpor),
	.devclrn(devclrn),
	.devoe(devoe));

rx_block u2(
	.rx_locked(\u2|altlvds_rx_component|auto_generated|wire_pll_locked ),
	.rx_outclock(\u2|altlvds_rx_component|auto_generated|rx_outclock_buf|wire_clkctrl3_outclk ),
	.rxreg_0(\u2|altlvds_rx_component|auto_generated|rxreg [0]),
	.rxreg_1(\u2|altlvds_rx_component|auto_generated|rxreg [1]),
	.rxreg_2(\u2|altlvds_rx_component|auto_generated|rxreg [2]),
	.rxreg_3(\u2|altlvds_rx_component|auto_generated|rxreg [3]),
	.rxreg_4(\u2|altlvds_rx_component|auto_generated|rxreg [4]),
	.rxreg_5(\u2|altlvds_rx_component|auto_generated|rxreg [5]),
	.rxreg_6(\u2|altlvds_rx_component|auto_generated|rxreg [6]),
	.rxreg_7(\u2|altlvds_rx_component|auto_generated|rxreg [7]),
	.rxreg_8(\u2|altlvds_rx_component|auto_generated|rxreg [8]),
	.rxreg_9(\u2|altlvds_rx_component|auto_generated|rxreg [9]),
	.test_rx_in(\test_rx_in~input_o ),
	.test_rx_inclock(\test_rx_inclock~input_o ),
	.wire_rx_divfwdclk_0(\u2|altlvds_rx_component|auto_generated|wire_rx_divfwdclk[0]~clkctrl_outclk ),
	.devpor(devpor),
	.devclrn(devclrn),
	.devoe(devoe));

recv_core_reg u7(
	.rxreg_0(\u2|altlvds_rx_component|auto_generated|rxreg [0]),
	.rxreg_1(\u2|altlvds_rx_component|auto_generated|rxreg [1]),
	.rxreg_2(\u2|altlvds_rx_component|auto_generated|rxreg [2]),
	.rxreg_3(\u2|altlvds_rx_component|auto_generated|rxreg [3]),
	.rxreg_4(\u2|altlvds_rx_component|auto_generated|rxreg [4]),
	.rxreg_5(\u2|altlvds_rx_component|auto_generated|rxreg [5]),
	.rxreg_6(\u2|altlvds_rx_component|auto_generated|rxreg [6]),
	.rxreg_7(\u2|altlvds_rx_component|auto_generated|rxreg [7]),
	.rxreg_8(\u2|altlvds_rx_component|auto_generated|rxreg [8]),
	.rxreg_9(\u2|altlvds_rx_component|auto_generated|rxreg [9]),
	.dffs_0(\u7|lpm_ff_component|dffs [0]),
	.dffs_1(\u7|lpm_ff_component|dffs [1]),
	.dffs_2(\u7|lpm_ff_component|dffs [2]),
	.dffs_3(\u7|lpm_ff_component|dffs [3]),
	.dffs_4(\u7|lpm_ff_component|dffs [4]),
	.dffs_5(\u7|lpm_ff_component|dffs [5]),
	.dffs_6(\u7|lpm_ff_component|dffs [6]),
	.dffs_7(\u7|lpm_ff_component|dffs [7]),
	.dffs_8(\u7|lpm_ff_component|dffs [8]),
	.dffs_9(\u7|lpm_ff_component|dffs [9]),
	.recv_reg_clk(\recv_reg_clk~inputclkctrl_outclk ),
	.devpor(devpor),
	.devclrn(devclrn),
	.devoe(devoe));

tran_core_reg u8(
	.dffs_0(\u7|lpm_ff_component|dffs [0]),
	.dffs_1(\u7|lpm_ff_component|dffs [1]),
	.dffs_2(\u7|lpm_ff_component|dffs [2]),
	.dffs_3(\u7|lpm_ff_component|dffs [3]),
	.dffs_4(\u7|lpm_ff_component|dffs [4]),
	.dffs_5(\u7|lpm_ff_component|dffs [5]),
	.dffs_6(\u7|lpm_ff_component|dffs [6]),
	.dffs_7(\u7|lpm_ff_component|dffs [7]),
	.dffs_8(\u7|lpm_ff_component|dffs [8]),
	.dffs_9(\u7|lpm_ff_component|dffs [9]),
	.dffs_01(\u8|lpm_ff_component|dffs [0]),
	.dffs_11(\u8|lpm_ff_component|dffs [1]),
	.dffs_21(\u8|lpm_ff_component|dffs [2]),
	.dffs_31(\u8|lpm_ff_component|dffs [3]),
	.dffs_41(\u8|lpm_ff_component|dffs [4]),
	.dffs_51(\u8|lpm_ff_component|dffs [5]),
	.dffs_61(\u8|lpm_ff_component|dffs [6]),
	.dffs_71(\u8|lpm_ff_component|dffs [7]),
	.dffs_81(\u8|lpm_ff_component|dffs [8]),
	.dffs_91(\u8|lpm_ff_component|dffs [9]),
	.tran_reg_clk(\tran_reg_clk~inputclkctrl_outclk ),
	.devpor(devpor),
	.devclrn(devclrn),
	.devoe(devoe));

// atom is at IOIBUF_X91_Y31_N1
stratixiii_io_ibuf \test_tx_inclock~input (
	.i(test_tx_inclock),
	.ibar(gnd),
	.o(\test_tx_inclock~input_o ));
// synopsys translate_off
defparam \test_tx_inclock~input .bus_hold = "false";
defparam \test_tx_inclock~input .simulate_z_as = "z";
// synopsys translate_on

// atom is at IOIBUF_X0_Y30_N1
stratixiii_io_ibuf \test_rx_in~input (
	.i(test_rx_in),
	.ibar(\test_rx_in(n) ),
	.o(\test_rx_in~input_o ));
// synopsys translate_off
defparam \test_rx_in~input .bus_hold = "false";
defparam \test_rx_in~input .simulate_z_as = "z";
// synopsys translate_on

// atom is at IOIBUF_X0_Y31_N1
stratixiii_io_ibuf \test_rx_inclock~input (
	.i(test_rx_inclock),
	.ibar(\test_rx_inclock(n) ),
	.o(\test_rx_inclock~input_o ));
// synopsys translate_off
defparam \test_rx_inclock~input .bus_hold = "false";
defparam \test_rx_inclock~input .simulate_z_as = "z";
// synopsys translate_on

// atom is at IOIBUF_X0_Y38_N1
stratixiii_io_ibuf \recv_reg_clk~input (
	.i(recv_reg_clk),
	.ibar(gnd),
	.o(\recv_reg_clk~input_o ));
// synopsys translate_off
defparam \recv_reg_clk~input .bus_hold = "false";
defparam \recv_reg_clk~input .simulate_z_as = "z";
// synopsys translate_on

// atom is at IOIBUF_X0_Y38_N32
stratixiii_io_ibuf \tran_reg_clk~input (
	.i(tran_reg_clk),
	.ibar(gnd),
	.o(\tran_reg_clk~input_o ));
// synopsys translate_off
defparam \tran_reg_clk~input .bus_hold = "false";
defparam \tran_reg_clk~input .simulate_z_as = "z";
// synopsys translate_on

// atom is at CLKCTRL_G3
stratixiii_clkena \recv_reg_clk~inputclkctrl (
	.inclk(\recv_reg_clk~input_o ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\recv_reg_clk~inputclkctrl_outclk ),
	.enaout());
// synopsys translate_off
defparam \recv_reg_clk~inputclkctrl .clock_type = "global clock";
defparam \recv_reg_clk~inputclkctrl .ena_register_mode = "falling edge";
// synopsys translate_on

// atom is at CLKCTRL_G2
stratixiii_clkena \tran_reg_clk~inputclkctrl (
	.inclk(\tran_reg_clk~input_o ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\tran_reg_clk~inputclkctrl_outclk ),
	.enaout());
// synopsys translate_off
defparam \tran_reg_clk~inputclkctrl .clock_type = "global clock";
defparam \tran_reg_clk~inputclkctrl .ena_register_mode = "falling edge";
// synopsys translate_on

// atom is at IOOBUF_X91_Y40_N51
stratixiii_io_obuf \test_tx_locked~output (
	.i(\u1|altlvds_tx_component|auto_generated|wire_pll_locked ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(test_tx_locked),
	.obar());
// synopsys translate_off
defparam \test_tx_locked~output .bus_hold = "false";
defparam \test_tx_locked~output .open_drain_output = "false";
defparam \test_tx_locked~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X0_Y25_N113
stratixiii_io_obuf \test_rx_divfwdclk~output (
	.i(\u2|altlvds_rx_component|auto_generated|wire_rx_divfwdclk[0]~clkctrl_outclk ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(test_rx_divfwdclk),
	.obar());
// synopsys translate_off
defparam \test_rx_divfwdclk~output .bus_hold = "false";
defparam \test_rx_divfwdclk~output .open_drain_output = "false";
defparam \test_rx_divfwdclk~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X0_Y25_N51
stratixiii_io_obuf \test_rx_locked~output (
	.i(\u2|altlvds_rx_component|auto_generated|wire_pll_locked ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(test_rx_locked),
	.obar());
// synopsys translate_off
defparam \test_rx_locked~output .bus_hold = "false";
defparam \test_rx_locked~output .open_drain_output = "false";
defparam \test_rx_locked~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X91_Y25_N20
stratixiii_io_obuf \test_rx_out[0]~output (
	.i(\u2|altlvds_rx_component|auto_generated|rxreg [0]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(test_rx_out[0]),
	.obar());
// synopsys translate_off
defparam \test_rx_out[0]~output .bus_hold = "false";
defparam \test_rx_out[0]~output .open_drain_output = "false";
defparam \test_rx_out[0]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X0_Y27_N113
stratixiii_io_obuf \test_rx_out[1]~output (
	.i(\u2|altlvds_rx_component|auto_generated|rxreg [1]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(test_rx_out[1]),
	.obar());
// synopsys translate_off
defparam \test_rx_out[1]~output .bus_hold = "false";
defparam \test_rx_out[1]~output .open_drain_output = "false";
defparam \test_rx_out[1]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X91_Y29_N51
stratixiii_io_obuf \test_rx_out[2]~output (
	.i(\u2|altlvds_rx_component|auto_generated|rxreg [2]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(test_rx_out[2]),
	.obar());
// synopsys translate_off
defparam \test_rx_out[2]~output .bus_hold = "false";
defparam \test_rx_out[2]~output .open_drain_output = "false";
defparam \test_rx_out[2]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X0_Y39_N95
stratixiii_io_obuf \test_rx_out[3]~output (
	.i(\u2|altlvds_rx_component|auto_generated|rxreg [3]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(test_rx_out[3]),
	.obar());
// synopsys translate_off
defparam \test_rx_out[3]~output .bus_hold = "false";
defparam \test_rx_out[3]~output .open_drain_output = "false";
defparam \test_rx_out[3]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X0_Y27_N51
stratixiii_io_obuf \test_rx_out[4]~output (
	.i(\u2|altlvds_rx_component|auto_generated|rxreg [4]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(test_rx_out[4]),
	.obar());
// synopsys translate_off
defparam \test_rx_out[4]~output .bus_hold = "false";
defparam \test_rx_out[4]~output .open_drain_output = "false";
defparam \test_rx_out[4]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X0_Y27_N82
stratixiii_io_obuf \test_rx_out[5]~output (
	.i(\u2|altlvds_rx_component|auto_generated|rxreg [5]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(test_rx_out[5]),
	.obar());
// synopsys translate_off
defparam \test_rx_out[5]~output .bus_hold = "false";
defparam \test_rx_out[5]~output .open_drain_output = "false";
defparam \test_rx_out[5]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X91_Y40_N20
stratixiii_io_obuf \test_rx_out[6]~output (
	.i(\u2|altlvds_rx_component|auto_generated|rxreg [6]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(test_rx_out[6]),
	.obar());
// synopsys translate_off
defparam \test_rx_out[6]~output .bus_hold = "false";
defparam \test_rx_out[6]~output .open_drain_output = "false";
defparam \test_rx_out[6]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X91_Y29_N82
stratixiii_io_obuf \test_rx_out[7]~output (
	.i(\u2|altlvds_rx_component|auto_generated|rxreg [7]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(test_rx_out[7]),
	.obar());
// synopsys translate_off
defparam \test_rx_out[7]~output .bus_hold = "false";
defparam \test_rx_out[7]~output .open_drain_output = "false";
defparam \test_rx_out[7]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X0_Y27_N20
stratixiii_io_obuf \test_rx_out[8]~output (
	.i(\u2|altlvds_rx_component|auto_generated|rxreg [8]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(test_rx_out[8]),
	.obar());
// synopsys translate_off
defparam \test_rx_out[8]~output .bus_hold = "false";
defparam \test_rx_out[8]~output .open_drain_output = "false";
defparam \test_rx_out[8]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X91_Y25_N51
stratixiii_io_obuf \test_rx_out[9]~output (
	.i(\u2|altlvds_rx_component|auto_generated|rxreg [9]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(test_rx_out[9]),
	.obar());
// synopsys translate_off
defparam \test_rx_out[9]~output .bus_hold = "false";
defparam \test_rx_out[9]~output .open_drain_output = "false";
defparam \test_rx_out[9]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X91_Y31_N33
stratixiii_io_obuf \test_tx_out~output (
	.i(\u1|altlvds_tx_component|auto_generated|wire_tx_dataout [0]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),