altlvds_s3_serial_link.vt

CPLD/FPGA常用模块与综合系统设计实例光盘程序

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors  
// are exported from a vector file in the Quartus Waveform Editor and apply to  
// the top level entity of the current Quartus project .The user can use this   
// testbench to simulate his design using a third-party simulation tool .       
// *****************************************************************************
// Generated on "09/10/2007 15:44:12"
                                                                                
// Verilog Test Bench (with test vectors) for design :                          altlvds_s3_serial_link
// 
// Simulation tool : 3rd Party
// 

`timescale 1 ps/ 1 ps
module altlvds_s3_serial_link_vlg_vec_tst();
// constants                                           
// general purpose registers
reg recv_reg_clk;
reg test_rx_in;
reg test_rx_inclock;
reg test_tx_inclock;
reg tran_reg_clk;
// wires                                               
wire [9:0] dataout_to_tran;
wire [9:0] parallel_core_data;
wire test_rx_divfwdclk;
wire test_rx_locked;
wire [9:0] test_rx_out;
wire test_rx_outclock;
wire test_tx_locked;
wire test_tx_out;

// assign statements (if any)                          
altlvds_s3_serial_link i1 (
// port map - connection between master ports and signals/registers   
	.dataout_to_tran(dataout_to_tran),
	.parallel_core_data(parallel_core_data),
	.recv_reg_clk(recv_reg_clk),
	.test_rx_divfwdclk(test_rx_divfwdclk),
	.test_rx_in(test_rx_in),
	.test_rx_inclock(test_rx_inclock),
	.test_rx_locked(test_rx_locked),
	.test_rx_out(test_rx_out),
	.test_rx_outclock(test_rx_outclock),
	.test_tx_inclock(test_tx_inclock),
	.test_tx_locked(test_tx_locked),
	.test_tx_out(test_tx_out),
	.tran_reg_clk(tran_reg_clk)
);
initial 
begin 
#1000000 $stop;
end 

// test_rx_inclock
always
begin
	test_rx_inclock = 1'b0;
	test_rx_inclock = #10000 1'b1;
	#10000;
end 

// test_rx_in
initial
begin
	test_rx_in = 1'b0;
	test_rx_in = #110379 1'b1;
	test_rx_in = #9667 1'b0;
	test_rx_in = #5046 1'b1;
	test_rx_in = #4912 1'b0;
	test_rx_in = #2500 1'b1;
	test_rx_in = #2500 1'b0;
	test_rx_in = #2500 1'b1;
	test_rx_in = #2474 1'b0;
	test_rx_in = #1307 1'b1;
	# 1250;
	repeat(2)
	begin
		test_rx_in = 1'b0;
		test_rx_in = #1250 1'b1;
		# 1250;
	end
	test_rx_in = 1'b0;
	test_rx_in = #1250 1'b1;
	test_rx_in = #1224 1'b0;
	test_rx_in = #1046 1'b1;
	# 1000;
	repeat(3)
	begin
		test_rx_in = 1'b0;
		test_rx_in = #1000 1'b1;
		# 1000;
	end
	test_rx_in = 1'b0;
	test_rx_in = #1000 1'b1;
	# 949;
	repeat(3)
	begin
		test_rx_in = 1'b0;
		test_rx_in = #1250 1'b1;
		# 1250;
	end
	test_rx_in = 1'b0;
	test_rx_in = #1250 1'b1;
	test_rx_in = #1249 1'b0;
	test_rx_in = #2538 1'b1;
	test_rx_in = #2500 1'b0;
	test_rx_in = #2500 1'b1;
	test_rx_in = #2474 1'b0;
	test_rx_in = #5000 1'b1;
	test_rx_in = #14998 1'b0;
end 

// recv_reg_clk
always
begin
	recv_reg_clk = 1'b0;
	recv_reg_clk = #5000 1'b1;
	#5000;
end 

// tran_reg_clk
always
begin
	tran_reg_clk = 1'b0;
	tran_reg_clk = #5000 1'b1;
	#5000;
end 

// test_tx_inclock
always
begin
	test_tx_inclock = 1'b0;
	test_tx_inclock = #10000 1'b1;
	#10000;
end 
endmodule