cii_altlvds_extpll.vo

CPLD/FPGA常用模块与综合系统设计实例光盘程序

defparam \tx_parallel_data[5]~I .input_power_up = "low";
defparam \tx_parallel_data[5]~I .input_register_mode = "none";
defparam \tx_parallel_data[5]~I .input_sync_reset = "none";
defparam \tx_parallel_data[5]~I .oe_async_reset = "none";
defparam \tx_parallel_data[5]~I .oe_power_up = "low";
defparam \tx_parallel_data[5]~I .oe_register_mode = "none";
defparam \tx_parallel_data[5]~I .oe_sync_reset = "none";
defparam \tx_parallel_data[5]~I .operation_mode = "input";
defparam \tx_parallel_data[5]~I .output_async_reset = "none";
defparam \tx_parallel_data[5]~I .output_power_up = "low";
defparam \tx_parallel_data[5]~I .output_register_mode = "none";
defparam \tx_parallel_data[5]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X2_Y17_N11
cycloneii_lcell_ff \inst4[24] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(gnd),
	.sdata(\tx_parallel_data~combout [24]),
	.aclr(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[24]));

// atom is at PIN_J16
cycloneii_io \tx_parallel_data[26]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\tx_parallel_data~combout [26]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(tx_parallel_data[26]));
// synopsys translate_off
defparam \tx_parallel_data[26]~I .input_async_reset = "none";
defparam \tx_parallel_data[26]~I .input_power_up = "low";
defparam \tx_parallel_data[26]~I .input_register_mode = "none";
defparam \tx_parallel_data[26]~I .input_sync_reset = "none";
defparam \tx_parallel_data[26]~I .oe_async_reset = "none";
defparam \tx_parallel_data[26]~I .oe_power_up = "low";
defparam \tx_parallel_data[26]~I .oe_register_mode = "none";
defparam \tx_parallel_data[26]~I .oe_sync_reset = "none";
defparam \tx_parallel_data[26]~I .operation_mode = "input";
defparam \tx_parallel_data[26]~I .output_async_reset = "none";
defparam \tx_parallel_data[26]~I .output_power_up = "low";
defparam \tx_parallel_data[26]~I .output_register_mode = "none";
defparam \tx_parallel_data[26]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X2_Y17_N1
cycloneii_lcell_ff \inst4[25] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(\inst4[25]~feeder_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[25]));

// atom is at PIN_J15
cycloneii_io \tx_parallel_data[27]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\tx_parallel_data~combout [27]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(tx_parallel_data[27]));
// synopsys translate_off
defparam \tx_parallel_data[27]~I .input_async_reset = "none";
defparam \tx_parallel_data[27]~I .input_power_up = "low";
defparam \tx_parallel_data[27]~I .input_register_mode = "none";
defparam \tx_parallel_data[27]~I .input_sync_reset = "none";
defparam \tx_parallel_data[27]~I .oe_async_reset = "none";
defparam \tx_parallel_data[27]~I .oe_power_up = "low";
defparam \tx_parallel_data[27]~I .oe_register_mode = "none";
defparam \tx_parallel_data[27]~I .oe_sync_reset = "none";
defparam \tx_parallel_data[27]~I .operation_mode = "input";
defparam \tx_parallel_data[27]~I .output_async_reset = "none";
defparam \tx_parallel_data[27]~I .output_power_up = "low";
defparam \tx_parallel_data[27]~I .output_register_mode = "none";
defparam \tx_parallel_data[27]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X3_Y16_N11
cycloneii_lcell_ff \inst4[16] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(\inst4[16]~feeder_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[16]));

// atom is at PIN_H15
cycloneii_io \tx_parallel_data[18]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\tx_parallel_data~combout [18]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(tx_parallel_data[18]));
// synopsys translate_off
defparam \tx_parallel_data[18]~I .input_async_reset = "none";
defparam \tx_parallel_data[18]~I .input_power_up = "low";
defparam \tx_parallel_data[18]~I .input_register_mode = "none";
defparam \tx_parallel_data[18]~I .input_sync_reset = "none";
defparam \tx_parallel_data[18]~I .oe_async_reset = "none";
defparam \tx_parallel_data[18]~I .oe_power_up = "low";
defparam \tx_parallel_data[18]~I .oe_register_mode = "none";
defparam \tx_parallel_data[18]~I .oe_sync_reset = "none";
defparam \tx_parallel_data[18]~I .operation_mode = "input";
defparam \tx_parallel_data[18]~I .output_async_reset = "none";
defparam \tx_parallel_data[18]~I .output_power_up = "low";
defparam \tx_parallel_data[18]~I .output_register_mode = "none";
defparam \tx_parallel_data[18]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X3_Y16_N31
cycloneii_lcell_ff \inst4[17] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(\inst4[17]~feeder_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[17]));

// atom is at PIN_H16
cycloneii_io \tx_parallel_data[19]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\tx_parallel_data~combout [19]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(tx_parallel_data[19]));
// synopsys translate_off
defparam \tx_parallel_data[19]~I .input_async_reset = "none";
defparam \tx_parallel_data[19]~I .input_power_up = "low";
defparam \tx_parallel_data[19]~I .input_register_mode = "none";
defparam \tx_parallel_data[19]~I .input_sync_reset = "none";
defparam \tx_parallel_data[19]~I .oe_async_reset = "none";
defparam \tx_parallel_data[19]~I .oe_power_up = "low";
defparam \tx_parallel_data[19]~I .oe_register_mode = "none";
defparam \tx_parallel_data[19]~I .oe_sync_reset = "none";
defparam \tx_parallel_data[19]~I .operation_mode = "input";
defparam \tx_parallel_data[19]~I .output_async_reset = "none";
defparam \tx_parallel_data[19]~I .output_power_up = "low";
defparam \tx_parallel_data[19]~I .output_register_mode = "none";
defparam \tx_parallel_data[19]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X2_Y16_N19
cycloneii_lcell_ff \inst4[8] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(\inst4[8]~feeder_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[8]));

// atom is at PIN_A7
cycloneii_io \tx_parallel_data[10]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\tx_parallel_data~combout [10]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(tx_parallel_data[10]));
// synopsys translate_off
defparam \tx_parallel_data[10]~I .input_async_reset = "none";
defparam \tx_parallel_data[10]~I .input_power_up = "low";
defparam \tx_parallel_data[10]~I .input_register_mode = "none";
defparam \tx_parallel_data[10]~I .input_sync_reset = "none";
defparam \tx_parallel_data[10]~I .oe_async_reset = "none";
defparam \tx_parallel_data[10]~I .oe_power_up = "low";
defparam \tx_parallel_data[10]~I .oe_register_mode = "none";
defparam \tx_parallel_data[10]~I .oe_sync_reset = "none";
defparam \tx_parallel_data[10]~I .operation_mode = "input";
defparam \tx_parallel_data[10]~I .output_async_reset = "none";
defparam \tx_parallel_data[10]~I .output_power_up = "low";
defparam \tx_parallel_data[10]~I .output_register_mode = "none";
defparam \tx_parallel_data[10]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X3_Y15_N7
cycloneii_lcell_ff \inst4[9] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(\inst4[9]~feeder_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[9]));

// atom is at PIN_T4
cycloneii_io \tx_parallel_data[11]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\tx_parallel_data~combout [11]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(tx_parallel_data[11]));
// synopsys translate_off
defparam \tx_parallel_data[11]~I .input_async_reset = "none";
defparam \tx_parallel_data[11]~I .input_power_up = "low";
defparam \tx_parallel_data[11]~I .input_register_mode = "none";
defparam \tx_parallel_data[11]~I .input_sync_reset = "none";
defparam \tx_parallel_data[11]~I .oe_async_reset = "none";
defparam \tx_parallel_data[11]~I .oe_power_up = "low";
defparam \tx_parallel_data[11]~I .oe_register_mode = "none";
defparam \tx_parallel_data[11]~I .oe_sync_reset = "none";
defparam \tx_parallel_data[11]~I .operation_mode = "input";
defparam \tx_parallel_data[11]~I .output_async_reset = "none";
defparam \tx_parallel_data[11]~I .output_power_up = "low";
defparam \tx_parallel_data[11]~I .output_register_mode = "none";
defparam \tx_parallel_data[11]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X3_Y15_N23
cycloneii_lcell_ff \inst4[0] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(\inst4[0]~feeder_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[0]));

// atom is at PIN_J4
cycloneii_io \tx_parallel_data[2]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\tx_parallel_data~combout [2]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(tx_parallel_data[2]));
// synopsys translate_off
defparam \tx_parallel_data[2]~I .input_async_reset = "none";
defparam \tx_parallel_data[2]~I .input_power_up = "low";
defparam \tx_parallel_data[2]~I .input_register_mode = "none";
defparam \tx_parallel_data[2]~I .input_sync_reset = "none";
defparam \tx_parallel_data[2]~I .oe_async_reset = "none";
defparam \tx_parallel_data[2]~I .oe_power_up = "low";
defparam \tx_parallel_data[2]~I .oe_register_mode = "none";
defparam \tx_parallel_data[2]~I .oe_sync_reset = "none";
defparam \tx_parallel_data[2]~I .operation_mode = "input";
defparam \tx_parallel_data[2]~I .output_async_reset = "none";
defparam \tx_parallel_data[2]~I .output_power_up = "low";
defparam \tx_parallel_data[2]~I .output_register_mode = "none";
defparam \tx_parallel_data[2]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X3_Y15_N19
cycloneii_lcell_ff \inst4[1] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(gnd),
	.sdata(\tx_parallel_data~combout [1]),
	.aclr(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.devclrn