cii_altlvds_extpll.vo

CPLD/FPGA常用模块与综合系统设计实例光盘程序

	.regout(inst4[26]));

// atom is at PIN_G10
cycloneii_io \tx_parallel_data[28]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\tx_parallel_data~combout [28]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(tx_parallel_data[28]));
// synopsys translate_off
defparam \tx_parallel_data[28]~I .input_async_reset = "none";
defparam \tx_parallel_data[28]~I .input_power_up = "low";
defparam \tx_parallel_data[28]~I .input_register_mode = "none";
defparam \tx_parallel_data[28]~I .input_sync_reset = "none";
defparam \tx_parallel_data[28]~I .oe_async_reset = "none";
defparam \tx_parallel_data[28]~I .oe_power_up = "low";
defparam \tx_parallel_data[28]~I .oe_register_mode = "none";
defparam \tx_parallel_data[28]~I .oe_sync_reset = "none";
defparam \tx_parallel_data[28]~I .operation_mode = "input";
defparam \tx_parallel_data[28]~I .output_async_reset = "none";
defparam \tx_parallel_data[28]~I .output_power_up = "low";
defparam \tx_parallel_data[28]~I .output_register_mode = "none";
defparam \tx_parallel_data[28]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X2_Y17_N15
cycloneii_lcell_ff \inst4[27] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(gnd),
	.sdata(\tx_parallel_data~combout [27]),
	.aclr(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[27]));

// atom is at PIN_B5
cycloneii_io \tx_parallel_data[29]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\tx_parallel_data~combout [29]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(tx_parallel_data[29]));
// synopsys translate_off
defparam \tx_parallel_data[29]~I .input_async_reset = "none";
defparam \tx_parallel_data[29]~I .input_power_up = "low";
defparam \tx_parallel_data[29]~I .input_register_mode = "none";
defparam \tx_parallel_data[29]~I .input_sync_reset = "none";
defparam \tx_parallel_data[29]~I .oe_async_reset = "none";
defparam \tx_parallel_data[29]~I .oe_power_up = "low";
defparam \tx_parallel_data[29]~I .oe_register_mode = "none";
defparam \tx_parallel_data[29]~I .oe_sync_reset = "none";
defparam \tx_parallel_data[29]~I .operation_mode = "input";
defparam \tx_parallel_data[29]~I .output_async_reset = "none";
defparam \tx_parallel_data[29]~I .output_power_up = "low";
defparam \tx_parallel_data[29]~I .output_register_mode = "none";
defparam \tx_parallel_data[29]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X3_Y16_N23
cycloneii_lcell_ff \inst4[18] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(\inst4[18]~feeder_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[18]));

// atom is at PIN_B7
cycloneii_io \tx_parallel_data[20]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\tx_parallel_data~combout [20]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(tx_parallel_data[20]));
// synopsys translate_off
defparam \tx_parallel_data[20]~I .input_async_reset = "none";
defparam \tx_parallel_data[20]~I .input_power_up = "low";
defparam \tx_parallel_data[20]~I .input_register_mode = "none";
defparam \tx_parallel_data[20]~I .input_sync_reset = "none";
defparam \tx_parallel_data[20]~I .oe_async_reset = "none";
defparam \tx_parallel_data[20]~I .oe_power_up = "low";
defparam \tx_parallel_data[20]~I .oe_register_mode = "none";
defparam \tx_parallel_data[20]~I .oe_sync_reset = "none";
defparam \tx_parallel_data[20]~I .operation_mode = "input";
defparam \tx_parallel_data[20]~I .output_async_reset = "none";
defparam \tx_parallel_data[20]~I .output_power_up = "low";
defparam \tx_parallel_data[20]~I .output_register_mode = "none";
defparam \tx_parallel_data[20]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X2_Y16_N5
cycloneii_lcell_ff \inst4[19] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(\inst4[19]~feeder_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[19]));

// atom is at PIN_M3
cycloneii_io \tx_parallel_data[21]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\tx_parallel_data~combout [21]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(tx_parallel_data[21]));
// synopsys translate_off
defparam \tx_parallel_data[21]~I .input_async_reset = "none";
defparam \tx_parallel_data[21]~I .input_power_up = "low";
defparam \tx_parallel_data[21]~I .input_register_mode = "none";
defparam \tx_parallel_data[21]~I .input_sync_reset = "none";
defparam \tx_parallel_data[21]~I .oe_async_reset = "none";
defparam \tx_parallel_data[21]~I .oe_power_up = "low";
defparam \tx_parallel_data[21]~I .oe_register_mode = "none";
defparam \tx_parallel_data[21]~I .oe_sync_reset = "none";
defparam \tx_parallel_data[21]~I .operation_mode = "input";
defparam \tx_parallel_data[21]~I .output_async_reset = "none";
defparam \tx_parallel_data[21]~I .output_power_up = "low";
defparam \tx_parallel_data[21]~I .output_register_mode = "none";
defparam \tx_parallel_data[21]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X2_Y16_N11
cycloneii_lcell_ff \inst4[10] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(\inst4[10]~feeder_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[10]));

// atom is at PIN_D8
cycloneii_io \tx_parallel_data[12]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\tx_parallel_data~combout [12]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(tx_parallel_data[12]));
// synopsys translate_off
defparam \tx_parallel_data[12]~I .input_async_reset = "none";
defparam \tx_parallel_data[12]~I .input_power_up = "low";
defparam \tx_parallel_data[12]~I .input_register_mode = "none";
defparam \tx_parallel_data[12]~I .input_sync_reset = "none";
defparam \tx_parallel_data[12]~I .oe_async_reset = "none";
defparam \tx_parallel_data[12]~I .oe_power_up = "low";
defparam \tx_parallel_data[12]~I .oe_register_mode = "none";
defparam \tx_parallel_data[12]~I .oe_sync_reset = "none";
defparam \tx_parallel_data[12]~I .operation_mode = "input";
defparam \tx_parallel_data[12]~I .output_async_reset = "none";
defparam \tx_parallel_data[12]~I .output_power_up = "low";
defparam \tx_parallel_data[12]~I .output_register_mode = "none";
defparam \tx_parallel_data[12]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X3_Y15_N17
cycloneii_lcell_ff \inst4[11] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(\inst4[11]~feeder_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[11]));

// atom is at PIN_B6
cycloneii_io \tx_parallel_data[13]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\tx_parallel_data~combout [13]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(tx_parallel_data[13]));
// synopsys translate_off
defparam \tx_parallel_data[13]~I .input_async_reset = "none";
defparam \tx_parallel_data[13]~I .input_power_up = "low";
defparam \tx_parallel_data[13]~I .input_register_mode = "none";
defparam \tx_parallel_data[13]~I .input_sync_reset = "none";
defparam \tx_parallel_data[13]~I .oe_async_reset = "none";
defparam \tx_parallel_data[13]~I .oe_power_up = "low";
defparam \tx_parallel_data[13]~I .oe_register_mode = "none";
defparam \tx_parallel_data[13]~I .oe_sync_reset = "none";
defparam \tx_parallel_data[13]~I .operation_mode = "input";
defparam \tx_parallel_data[13]~I .output_async_reset = "none";
defparam \tx_parallel_data[13]~I .output_power_up = "low";
defparam \tx_parallel_data[13]~I .output_register_mode = "none";
defparam \tx_parallel_data[13]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X2_Y15_N31
cycloneii_lcell_ff \inst4[2] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(\inst4[2]~feeder_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[2]));

// atom is at PIN_N2
cycloneii_io \tx_parallel_data[4]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\tx_parallel_data~combout [4]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(tx_parallel_data[4]));
// synopsys translate_off
defparam \tx_parallel_data[4]~I .input_async_reset = "none";
defparam \tx_parallel_data[4]~I .input_power_up = "low";
defparam \tx_parallel_data[4]~I .input_register_mode = "none";
defparam \tx_parallel_data[4]~I .input_sync_reset = "none";
defparam \tx_parallel_data[4]~I .oe_async_reset = "none";
defparam \tx_parallel_data[4]~I .oe_power_up = "low";
defparam \tx_parallel_data[4]~I .oe_register_mode = "none";
defparam \tx_parallel_data[4]~I .oe_sync_reset = "none";
defparam \tx_parallel_data[4]~I .operation_mode = "input";
defparam \tx_parallel_data[4]~I .output_async_reset = "none";
defparam \tx_parallel_data[4]~I .output_power_up = "low";
defparam \tx_parallel_data[4]~I .output_register_mode = "none";
defparam \tx_parallel_data[4]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X3_Y15_N13
cycloneii_lcell_ff \inst4[3] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(\inst4[3]~feeder_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[3]));

// atom is at PIN_M2
cycloneii_io \tx_parallel_data[5]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\tx_parallel_data~combout [5]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(tx_parallel_data[5]));
// synopsys translate_off
defparam \tx_parallel_data[5]~I .input_async_reset = "none";