cii_altlvds_extpll.vo

CPLD/FPGA常用模块与综合系统设计实例光盘程序

defparam \tx_parallel_data[30]~I .input_register_mode = "none";
defparam \tx_parallel_data[30]~I .input_sync_reset = "none";
defparam \tx_parallel_data[30]~I .oe_async_reset = "none";
defparam \tx_parallel_data[30]~I .oe_power_up = "low";
defparam \tx_parallel_data[30]~I .oe_register_mode = "none";
defparam \tx_parallel_data[30]~I .oe_sync_reset = "none";
defparam \tx_parallel_data[30]~I .operation_mode = "input";
defparam \tx_parallel_data[30]~I .output_async_reset = "none";
defparam \tx_parallel_data[30]~I .output_power_up = "low";
defparam \tx_parallel_data[30]~I .output_register_mode = "none";
defparam \tx_parallel_data[30]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X2_Y17_N19
cycloneii_lcell_ff \inst4[29] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(\inst4[29]~feeder_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[29]));

// atom is at PIN_D6
cycloneii_io \tx_parallel_data[31]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\tx_parallel_data~combout [31]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(tx_parallel_data[31]));
// synopsys translate_off
defparam \tx_parallel_data[31]~I .input_async_reset = "none";
defparam \tx_parallel_data[31]~I .input_power_up = "low";
defparam \tx_parallel_data[31]~I .input_register_mode = "none";
defparam \tx_parallel_data[31]~I .input_sync_reset = "none";
defparam \tx_parallel_data[31]~I .oe_async_reset = "none";
defparam \tx_parallel_data[31]~I .oe_power_up = "low";
defparam \tx_parallel_data[31]~I .oe_register_mode = "none";
defparam \tx_parallel_data[31]~I .oe_sync_reset = "none";
defparam \tx_parallel_data[31]~I .operation_mode = "input";
defparam \tx_parallel_data[31]~I .output_async_reset = "none";
defparam \tx_parallel_data[31]~I .output_power_up = "low";
defparam \tx_parallel_data[31]~I .output_register_mode = "none";
defparam \tx_parallel_data[31]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X3_Y16_N27
cycloneii_lcell_ff \inst4[20] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(gnd),
	.sdata(\tx_parallel_data~combout [20]),
	.aclr(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[20]));

// atom is at PIN_L3
cycloneii_io \tx_parallel_data[22]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\tx_parallel_data~combout [22]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(tx_parallel_data[22]));
// synopsys translate_off
defparam \tx_parallel_data[22]~I .input_async_reset = "none";
defparam \tx_parallel_data[22]~I .input_power_up = "low";
defparam \tx_parallel_data[22]~I .input_register_mode = "none";
defparam \tx_parallel_data[22]~I .input_sync_reset = "none";
defparam \tx_parallel_data[22]~I .oe_async_reset = "none";
defparam \tx_parallel_data[22]~I .oe_power_up = "low";
defparam \tx_parallel_data[22]~I .oe_register_mode = "none";
defparam \tx_parallel_data[22]~I .oe_sync_reset = "none";
defparam \tx_parallel_data[22]~I .operation_mode = "input";
defparam \tx_parallel_data[22]~I .output_async_reset = "none";
defparam \tx_parallel_data[22]~I .output_power_up = "low";
defparam \tx_parallel_data[22]~I .output_register_mode = "none";
defparam \tx_parallel_data[22]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X2_Y16_N9
cycloneii_lcell_ff \inst4[21] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(gnd),
	.sdata(\tx_parallel_data~combout [21]),
	.aclr(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[21]));

// atom is at PIN_N1
cycloneii_io \tx_parallel_data[23]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\tx_parallel_data~combout [23]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(tx_parallel_data[23]));
// synopsys translate_off
defparam \tx_parallel_data[23]~I .input_async_reset = "none";
defparam \tx_parallel_data[23]~I .input_power_up = "low";
defparam \tx_parallel_data[23]~I .input_register_mode = "none";
defparam \tx_parallel_data[23]~I .input_sync_reset = "none";
defparam \tx_parallel_data[23]~I .oe_async_reset = "none";
defparam \tx_parallel_data[23]~I .oe_power_up = "low";
defparam \tx_parallel_data[23]~I .oe_register_mode = "none";
defparam \tx_parallel_data[23]~I .oe_sync_reset = "none";
defparam \tx_parallel_data[23]~I .operation_mode = "input";
defparam \tx_parallel_data[23]~I .output_async_reset = "none";
defparam \tx_parallel_data[23]~I .output_power_up = "low";
defparam \tx_parallel_data[23]~I .output_register_mode = "none";
defparam \tx_parallel_data[23]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X2_Y16_N17
cycloneii_lcell_ff \inst4[12] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(gnd),
	.sdata(\tx_parallel_data~combout [12]),
	.aclr(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[12]));

// atom is at PIN_C6
cycloneii_io \tx_parallel_data[14]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\tx_parallel_data~combout [14]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(tx_parallel_data[14]));
// synopsys translate_off
defparam \tx_parallel_data[14]~I .input_async_reset = "none";
defparam \tx_parallel_data[14]~I .input_power_up = "low";
defparam \tx_parallel_data[14]~I .input_register_mode = "none";
defparam \tx_parallel_data[14]~I .input_sync_reset = "none";
defparam \tx_parallel_data[14]~I .oe_async_reset = "none";
defparam \tx_parallel_data[14]~I .oe_power_up = "low";
defparam \tx_parallel_data[14]~I .oe_register_mode = "none";
defparam \tx_parallel_data[14]~I .oe_sync_reset = "none";
defparam \tx_parallel_data[14]~I .operation_mode = "input";
defparam \tx_parallel_data[14]~I .output_async_reset = "none";
defparam \tx_parallel_data[14]~I .output_power_up = "low";
defparam \tx_parallel_data[14]~I .output_register_mode = "none";
defparam \tx_parallel_data[14]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X4_Y15_N27
cycloneii_lcell_ff \inst4[13] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(\inst4[13]~feeder_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[13]));

// atom is at PIN_L2
cycloneii_io \tx_parallel_data[15]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\tx_parallel_data~combout [15]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(tx_parallel_data[15]));
// synopsys translate_off
defparam \tx_parallel_data[15]~I .input_async_reset = "none";
defparam \tx_parallel_data[15]~I .input_power_up = "low";
defparam \tx_parallel_data[15]~I .input_register_mode = "none";
defparam \tx_parallel_data[15]~I .input_sync_reset = "none";
defparam \tx_parallel_data[15]~I .oe_async_reset = "none";
defparam \tx_parallel_data[15]~I .oe_power_up = "low";
defparam \tx_parallel_data[15]~I .oe_register_mode = "none";
defparam \tx_parallel_data[15]~I .oe_sync_reset = "none";
defparam \tx_parallel_data[15]~I .operation_mode = "input";
defparam \tx_parallel_data[15]~I .output_async_reset = "none";
defparam \tx_parallel_data[15]~I .output_power_up = "low";
defparam \tx_parallel_data[15]~I .output_register_mode = "none";
defparam \tx_parallel_data[15]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X2_Y15_N13
cycloneii_lcell_ff \inst4[4] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(\inst4[4]~feeder_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[4]));

// atom is at PIN_M1
cycloneii_io \tx_parallel_data[6]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\tx_parallel_data~combout [6]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(tx_parallel_data[6]));
// synopsys translate_off
defparam \tx_parallel_data[6]~I .input_async_reset = "none";
defparam \tx_parallel_data[6]~I .input_power_up = "low";
defparam \tx_parallel_data[6]~I .input_register_mode = "none";
defparam \tx_parallel_data[6]~I .input_sync_reset = "none";
defparam \tx_parallel_data[6]~I .oe_async_reset = "none";
defparam \tx_parallel_data[6]~I .oe_power_up = "low";
defparam \tx_parallel_data[6]~I .oe_register_mode = "none";
defparam \tx_parallel_data[6]~I .oe_sync_reset = "none";
defparam \tx_parallel_data[6]~I .operation_mode = "input";
defparam \tx_parallel_data[6]~I .output_async_reset = "none";
defparam \tx_parallel_data[6]~I .output_power_up = "low";
defparam \tx_parallel_data[6]~I .output_register_mode = "none";
defparam \tx_parallel_data[6]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X2_Y15_N15
cycloneii_lcell_ff \inst4[5] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(gnd),
	.sdata(\tx_parallel_data~combout [5]),
	.aclr(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[5]));

// atom is at PIN_A5
cycloneii_io \tx_parallel_data[7]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\tx_parallel_data~combout [7]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(tx_parallel_data[7]));
// synopsys translate_off
defparam \tx_parallel_data[7]~I .input_async_reset = "none";
defparam \tx_parallel_data[7]~I .input_power_up = "low";
defparam \tx_parallel_data[7]~I .input_register_mode = "none";
defparam \tx_parallel_data[7]~I .input_sync_reset = "none";
defparam \tx_parallel_data[7]~I .oe_async_reset = "none";
defparam \tx_parallel_data[7]~I .oe_power_up = "low";
defparam \tx_parallel_data[7]~I .oe_register_mode = "none";
defparam \tx_parallel_data[7]~I .oe_sync_reset = "none";
defparam \tx_parallel_data[7]~I .operation_mode = "input";
defparam \tx_parallel_data[7]~I .output_async_reset = "none";
defparam \tx_parallel_data[7]~I .output_power_up = "low";
defparam \tx_parallel_data[7]~I .output_register_mode = "none";
defparam \tx_parallel_data[7]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X2_Y17_N23
cycloneii_lcell_ff \inst4[26] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(gnd),
	.sdata(\tx_parallel_data~combout [26]),
	.aclr(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),