cii_altlvds_extpll.vo

CPLD/FPGA常用模块与综合系统设计实例光盘程序

defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_2~I .operation_mode = "input";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_2~I .output_async_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_2~I .output_power_up = "low";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_2~I .output_register_mode = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_2~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_J6
cycloneii_io \inst|altlvds_rx_component|auto_generated|ddio_in_posa_1~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(\inst2|altpll_component|_clk0~clkctrl_outclk ),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(\inst|altlvds_rx_component|auto_generated|wire_ddio_in_posa_regout [1]),
	.differentialout(\inst|altlvds_rx_component|auto_generated|wire_ddio_in_nega_differentialin [1]),
	.linkout(),
	.padio(rx_in[1]));
// synopsys translate_off
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_1~I .input_async_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_1~I .input_power_up = "low";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_1~I .input_register_mode = "register";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_1~I .input_sync_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_1~I .oe_async_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_1~I .oe_power_up = "low";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_1~I .oe_register_mode = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_1~I .oe_sync_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_1~I .operation_mode = "input";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_1~I .output_async_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_1~I .output_power_up = "low";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_1~I .output_register_mode = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_1~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_C1
cycloneii_io \inst|altlvds_rx_component|auto_generated|ddio_in_posa_0~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(\inst2|altpll_component|_clk0~clkctrl_outclk ),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(\inst|altlvds_rx_component|auto_generated|wire_ddio_in_posa_regout [0]),
	.differentialout(\inst|altlvds_rx_component|auto_generated|wire_ddio_in_nega_differentialin [0]),
	.linkout(),
	.padio(rx_in[0]));
// synopsys translate_off
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_0~I .input_async_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_0~I .input_power_up = "low";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_0~I .input_register_mode = "register";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_0~I .input_sync_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_0~I .oe_async_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_0~I .oe_power_up = "low";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_0~I .oe_register_mode = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_0~I .oe_sync_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_0~I .operation_mode = "input";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_0~I .output_async_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_0~I .output_power_up = "low";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_0~I .output_register_mode = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_0~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X2_Y17_N21
cycloneii_lcell_ff \inst4[30] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(\inst4[30]~feeder_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[30]));

// atom is at LCFF_X2_Y17_N9
cycloneii_lcell_ff \inst4[31] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(\inst4[31]~feeder_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[31]));

// atom is at LCFF_X1_Y16_N13
cycloneii_lcell_ff \inst4[22] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(\inst4[22]~feeder_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[22]));

// atom is at LCFF_X2_Y16_N3
cycloneii_lcell_ff \inst4[23] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(gnd),
	.sdata(\tx_parallel_data~combout [23]),
	.aclr(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[23]));

// atom is at LCFF_X2_Y16_N7
cycloneii_lcell_ff \inst4[14] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(\inst4[14]~feeder_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[14]));

// atom is at LCFF_X2_Y15_N7
cycloneii_lcell_ff \inst4[15] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(\inst4[15]~feeder_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[15]));

// atom is at LCFF_X2_Y15_N11
cycloneii_lcell_ff \inst4[6] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(\inst4[6]~feeder_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[6]));

// atom is at LCFF_X2_Y15_N25
cycloneii_lcell_ff \inst4[7] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(gnd),
	.sdata(\tx_parallel_data~combout [7]),
	.aclr(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[7]));

// atom is at PIN_E2
cycloneii_io \inst|altlvds_rx_component|auto_generated|ddio_in_nega_3~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(!\inst2|altpll_component|_clk0~clkctrl_outclk ),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(\inst|altlvds_rx_component|auto_generated|wire_ddio_in_nega_differentialin [3]),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(\inst|altlvds_rx_component|auto_generated|wire_ddio_in_nega_regout [3]),
	.differentialout(),
	.linkout(),
	.padio());
// synopsys translate_off
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_3~I .input_async_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_3~I .input_power_up = "low";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_3~I .input_register_mode = "register";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_3~I .input_sync_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_3~I .oe_async_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_3~I .oe_power_up = "low";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_3~I .oe_register_mode = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_3~I .oe_sync_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_3~I .operation_mode = "input";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_3~I .output_async_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_3~I .output_power_up = "low";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_3~I .output_register_mode = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_3~I .output_sync_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_3~I .use_differential_input = "true";
// synopsys translate_on

// atom is at PIN_K1
cycloneii_io \inst|altlvds_rx_component|auto_generated|ddio_in_nega_2~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(!\inst2|altpll_component|_clk0~clkctrl_outclk ),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(\inst|altlvds_rx_component|auto_generated|wire_ddio_in_nega_differentialin [2]),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(\inst|altlvds_rx_component|auto_generated|wire_ddio_in_nega_regout [2]),
	.differentialout(),
	.linkout(),
	.padio());
// synopsys translate_off
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_2~I .input_async_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_2~I .input_power_up = "low";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_2~I .input_register_mode = "register";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_2~I .input_sync_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_2~I .oe_async_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_2~I .oe_power_up = "low";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_2~I .oe_register_mode = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_2~I .oe_sync_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_2~I .operation_mode = "input";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_2~I .output_async_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_2~I .output_power_up = "low";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_2~I .output_register_mode = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_2~I .output_sync_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_2~I .use_differential_input = "true";
// synopsys translate_on

// atom is at PIN_H6
cycloneii_io \inst|altlvds_rx_component|auto_generated|ddio_in_nega_1~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(!\inst2|altpll_component|_clk0~clkctrl_outclk ),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(\inst|altlvds_rx_component|auto_generated|wire_ddio_in_nega_differentialin [1]),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(\inst|altlvds_rx_component|auto_generated|wire_ddio_in_nega_regout [1]),
	.differentialout(),
	.linkout(),
	.padio());
// synopsys translate_off
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_1~I .input_async_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_1~I .input_power_up = "low";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_1~I .input_register_mode = "register";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_1~I .input_sync_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_1~I .oe_async_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_1~I .oe_power_up = "low";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_1~I .oe_register_mode = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_1~I .oe_sync_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_1~I .operation_mode = "input";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_1~I .output_async_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_1~I .output_power_up = "low";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_1~I .output_register_mode = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_1~I .output_sync_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_1~I .use_differential_input = "true";
// synopsys translate_on

// atom is at PIN_C2
cycloneii_io \inst|altlvds_rx_component|auto_generated|ddio_in_nega_0~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(!\inst2|altpll_component|_clk0~clkctrl_outclk ),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(\inst|altlvds_rx_component|auto_generated|wire_ddio_in_nega_differentialin [0]),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(\inst|altlvds_rx_component|auto_generated|wire_ddio_in_nega_regout [0]),
	.differentialout(),
	.linkout(),
	.padio());
// synopsys translate_off
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_0~I .input_async_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_0~I .input_power_up = "low";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_0~I .input_register_mode = "register";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_0~I .input_sync_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_0~I .oe_async_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_0~I .oe_power_up = "low";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_0~I .oe_register_mode = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_0~I .oe_sync_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_0~I .operation_mode = "input";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_0~I .output_async_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_0~I .output_power_up = "low";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_0~I .output_register_mode = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_0~I .output_sync_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_nega_0~I .use_differential_input = "true";
// synopsys translate_on

// atom is at LCFF_X2_Y17_N5
cycloneii_lcell_ff \inst4[28] (
	.clk(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.datain(\inst4[28]~feeder_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(inst4[28]));

// atom is at PIN_A4
cycloneii_io \tx_parallel_data[30]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\tx_parallel_data~combout [30]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(tx_parallel_data[30]));
// synopsys translate_off
defparam \tx_parallel_data[30]~I .input_async_reset = "none";
defparam \tx_parallel_data[30]~I .input_power_up = "low";