cii_altlvds_extpll.vo

CPLD/FPGA常用模块与综合系统设计实例光盘程序

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 7.2 Internal Build 120 07/26/2007 SJ Full Version"

// DATE "09/05/2007 21:32:06"

// 
// Device: Altera EP2C8F256C6 Package FBGA256
// 

// 
// This Verilog file should be used for ModelSim-Altera (Verilog) only
// 

`timescale 1 ps/ 1 ps

module cii_altlvds_extpll (
	pll_lock,
	ref_clock,
	pll_reset,
	slow_clock,
	rx_parallel_out,
	rx_in,
	tx_out,
	tx_parallel_data);
output 	pll_lock;
input 	ref_clock;
input 	pll_reset;
output 	slow_clock;
output 	[31:0] rx_parallel_out;
input 	[3:0] rx_in;
output 	[3:0] tx_out;
input 	[31:0] tx_parallel_data;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \inst2|altpll_component|_locked ;
wire \inst2|altpll_component|_clk1 ;
wire \pll_reset~combout ;
wire \ref_clock~combout ;
wire \inst2|altpll_component|_clk0~clkctrl_outclk ;
wire \inst2|altpll_component|_clk1~clkctrl_outclk ;
wire \inst4[30]~feeder_combout ;
wire \inst4[31]~feeder_combout ;
wire \inst4[22]~feeder_combout ;
wire \inst4[14]~feeder_combout ;
wire \inst4[15]~feeder_combout ;
wire \inst4[6]~feeder_combout ;
wire \inst4[28]~feeder_combout ;
wire \inst4[29]~feeder_combout ;
wire \inst4[13]~feeder_combout ;
wire \inst4[4]~feeder_combout ;
wire \inst4[18]~feeder_combout ;
wire \inst4[19]~feeder_combout ;
wire \inst4[10]~feeder_combout ;
wire \inst4[11]~feeder_combout ;
wire \inst4[2]~feeder_combout ;
wire \inst4[3]~feeder_combout ;
wire \inst4[25]~feeder_combout ;
wire \inst4[16]~feeder_combout ;
wire \inst4[17]~feeder_combout ;
wire \inst4[8]~feeder_combout ;
wire \inst4[9]~feeder_combout ;
wire \inst4[0]~feeder_combout ;
wire \slow_clock~clkctrl_e_outclk ;
wire \inst3[31]~feeder_combout ;
wire \inst3[30]~feeder_combout ;
wire \inst3[29]~feeder_combout ;
wire \inst3[28]~feeder_combout ;
wire \inst3[27]~feeder_combout ;
wire \inst3[25]~feeder_combout ;
wire \inst3[24]~feeder_combout ;
wire \inst3[23]~feeder_combout ;
wire \inst3[22]~feeder_combout ;
wire \inst3[21]~feeder_combout ;
wire \inst3[20]~feeder_combout ;
wire \inst3[19]~feeder_combout ;
wire \inst3[18]~feeder_combout ;
wire \inst3[17]~feeder_combout ;
wire \inst3[16]~feeder_combout ;
wire \inst3[15]~feeder_combout ;
wire \inst3[14]~feeder_combout ;
wire \inst3[13]~feeder_combout ;
wire \inst3[12]~feeder_combout ;
wire \inst3[11]~feeder_combout ;
wire \inst3[10]~feeder_combout ;
wire \inst3[9]~feeder_combout ;
wire \inst3[8]~feeder_combout ;
wire \inst3[7]~feeder_combout ;
wire \inst3[6]~feeder_combout ;
wire \inst3[5]~feeder_combout ;
wire \inst3[4]~feeder_combout ;
wire \inst3[3]~feeder_combout ;
wire \inst3[2]~feeder_combout ;
wire \inst3[1]~feeder_combout ;
wire \inst3[0]~feeder_combout ;
wire [3:0] \inst1|altlvds_tx_component|auto_generated|ddio_out|wire_muxa_combout ;
wire [3:0] \inst|altlvds_rx_component|auto_generated|dffe1a ;
wire [3:0] \inst|altlvds_rx_component|auto_generated|dffe2a ;
wire [3:0] \inst|altlvds_rx_component|auto_generated|dffe3a ;
wire [3:0] \inst|altlvds_rx_component|auto_generated|dffe4a ;
wire [3:0] \inst|altlvds_rx_component|auto_generated|dffe5a ;
wire [3:0] \inst|altlvds_rx_component|auto_generated|dffe6a ;
wire [3:0] \inst|altlvds_rx_component|auto_generated|dffe7a ;
wire [3:0] \inst|altlvds_rx_component|auto_generated|dffe8a ;
wire [3:0] \inst|altlvds_rx_component|auto_generated|wire_ddio_in_nega_differentialin ;
wire [3:0] \inst|altlvds_rx_component|auto_generated|wire_ddio_in_nega_regout ;
wire [3:0] \inst|altlvds_rx_component|auto_generated|wire_ddio_in_posa_regout ;
wire [31:0] inst3;
wire [31:0] inst4;
wire [31:0] \tx_parallel_data~combout ;


lvds_pll inst2(
	._locked(\inst2|altpll_component|_locked ),
	._clk1(\inst2|altpll_component|_clk1 ),
	.pll_reset(\pll_reset~combout ),
	.ref_clock(\ref_clock~combout ),
	._clk0(\inst2|altpll_component|_clk0~clkctrl_outclk ),
	._clk11(\inst2|altpll_component|_clk1~clkctrl_outclk ),
	.devpor(devpor),
	.devclrn(devclrn),
	.devoe(devoe));

rx_block inst(
	.dffe7a_3(\inst|altlvds_rx_component|auto_generated|dffe7a [3]),
	.dffe8a_3(\inst|altlvds_rx_component|auto_generated|dffe8a [3]),
	.dffe7a_2(\inst|altlvds_rx_component|auto_generated|dffe7a [2]),
	.dffe8a_2(\inst|altlvds_rx_component|auto_generated|dffe8a [2]),
	.dffe7a_1(\inst|altlvds_rx_component|auto_generated|dffe7a [1]),
	.dffe8a_1(\inst|altlvds_rx_component|auto_generated|dffe8a [1]),
	.dffe7a_0(\inst|altlvds_rx_component|auto_generated|dffe7a [0]),
	.dffe8a_0(\inst|altlvds_rx_component|auto_generated|dffe8a [0]),
	.dffe5a_3(\inst|altlvds_rx_component|auto_generated|dffe5a [3]),
	.dffe6a_3(\inst|altlvds_rx_component|auto_generated|dffe6a [3]),
	.dffe5a_2(\inst|altlvds_rx_component|auto_generated|dffe5a [2]),
	.dffe6a_2(\inst|altlvds_rx_component|auto_generated|dffe6a [2]),
	.dffe5a_1(\inst|altlvds_rx_component|auto_generated|dffe5a [1]),
	.dffe6a_1(\inst|altlvds_rx_component|auto_generated|dffe6a [1]),
	.dffe5a_0(\inst|altlvds_rx_component|auto_generated|dffe5a [0]),
	.dffe6a_0(\inst|altlvds_rx_component|auto_generated|dffe6a [0]),
	.dffe3a_3(\inst|altlvds_rx_component|auto_generated|dffe3a [3]),
	.dffe4a_3(\inst|altlvds_rx_component|auto_generated|dffe4a [3]),
	.dffe3a_2(\inst|altlvds_rx_component|auto_generated|dffe3a [2]),
	.dffe4a_2(\inst|altlvds_rx_component|auto_generated|dffe4a [2]),
	.dffe3a_1(\inst|altlvds_rx_component|auto_generated|dffe3a [1]),
	.dffe4a_1(\inst|altlvds_rx_component|auto_generated|dffe4a [1]),
	.dffe3a_0(\inst|altlvds_rx_component|auto_generated|dffe3a [0]),
	.dffe4a_0(\inst|altlvds_rx_component|auto_generated|dffe4a [0]),
	.dffe1a_3(\inst|altlvds_rx_component|auto_generated|dffe1a [3]),
	.dffe2a_3(\inst|altlvds_rx_component|auto_generated|dffe2a [3]),
	.dffe1a_2(\inst|altlvds_rx_component|auto_generated|dffe1a [2]),
	.dffe2a_2(\inst|altlvds_rx_component|auto_generated|dffe2a [2]),
	.dffe1a_1(\inst|altlvds_rx_component|auto_generated|dffe1a [1]),
	.dffe2a_1(\inst|altlvds_rx_component|auto_generated|dffe2a [1]),
	.dffe1a_0(\inst|altlvds_rx_component|auto_generated|dffe1a [0]),
	.dffe2a_0(\inst|altlvds_rx_component|auto_generated|dffe2a [0]),
	.wire_ddio_in_posa_regout_3(\inst|altlvds_rx_component|auto_generated|wire_ddio_in_posa_regout [3]),
	.wire_ddio_in_posa_regout_2(\inst|altlvds_rx_component|auto_generated|wire_ddio_in_posa_regout [2]),
	.wire_ddio_in_posa_regout_1(\inst|altlvds_rx_component|auto_generated|wire_ddio_in_posa_regout [1]),
	.wire_ddio_in_posa_regout_0(\inst|altlvds_rx_component|auto_generated|wire_ddio_in_posa_regout [0]),
	.wire_ddio_in_nega_regout_3(\inst|altlvds_rx_component|auto_generated|wire_ddio_in_nega_regout [3]),
	.wire_ddio_in_nega_regout_2(\inst|altlvds_rx_component|auto_generated|wire_ddio_in_nega_regout [2]),
	.wire_ddio_in_nega_regout_1(\inst|altlvds_rx_component|auto_generated|wire_ddio_in_nega_regout [1]),
	.wire_ddio_in_nega_regout_0(\inst|altlvds_rx_component|auto_generated|wire_ddio_in_nega_regout [0]),
	.rx_inclock(\inst2|altpll_component|_clk0~clkctrl_outclk ),
	.devpor(devpor),
	.devclrn(devclrn),
	.devoe(devoe));

tx_block inst1(
	.wire_muxa_combout_3(\inst1|altlvds_tx_component|auto_generated|ddio_out|wire_muxa_combout [3]),
	.wire_muxa_combout_2(\inst1|altlvds_tx_component|auto_generated|ddio_out|wire_muxa_combout [2]),
	.wire_muxa_combout_1(\inst1|altlvds_tx_component|auto_generated|ddio_out|wire_muxa_combout [1]),
	.wire_muxa_combout_0(\inst1|altlvds_tx_component|auto_generated|ddio_out|wire_muxa_combout [0]),
	.inst4_30(inst4[30]),
	.inst4_31(inst4[31]),
	.inst4_22(inst4[22]),
	.inst4_23(inst4[23]),
	.inst4_14(inst4[14]),
	.inst4_15(inst4[15]),
	.inst4_6(inst4[6]),
	.inst4_7(inst4[7]),
	.inst4_28(inst4[28]),
	.inst4_29(inst4[29]),
	.inst4_20(inst4[20]),
	.inst4_21(inst4[21]),
	.inst4_12(inst4[12]),
	.inst4_13(inst4[13]),
	.inst4_4(inst4[4]),
	.inst4_5(inst4[5]),
	.inst4_26(inst4[26]),
	.inst4_27(inst4[27]),
	.inst4_18(inst4[18]),
	.inst4_19(inst4[19]),
	.inst4_10(inst4[10]),
	.inst4_11(inst4[11]),
	.inst4_2(inst4[2]),
	.inst4_3(inst4[3]),
	.inst4_24(inst4[24]),
	.inst4_25(inst4[25]),
	.inst4_16(inst4[16]),
	.inst4_17(inst4[17]),
	.inst4_8(inst4[8]),
	.inst4_9(inst4[9]),
	.inst4_0(inst4[0]),
	.inst4_1(inst4[1]),
	._clk0(\inst2|altpll_component|_clk0~clkctrl_outclk ),
	.devpor(devpor),
	.devclrn(devclrn),
	.devoe(devoe));

// atom is at PIN_P5
cycloneii_io \pll_reset~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\pll_reset~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(pll_reset));
// synopsys translate_off
defparam \pll_reset~I .input_async_reset = "none";
defparam \pll_reset~I .input_power_up = "low";
defparam \pll_reset~I .input_register_mode = "none";
defparam \pll_reset~I .input_sync_reset = "none";
defparam \pll_reset~I .oe_async_reset = "none";
defparam \pll_reset~I .oe_power_up = "low";
defparam \pll_reset~I .oe_register_mode = "none";
defparam \pll_reset~I .oe_sync_reset = "none";
defparam \pll_reset~I .operation_mode = "input";
defparam \pll_reset~I .output_async_reset = "none";
defparam \pll_reset~I .output_power_up = "low";
defparam \pll_reset~I .output_register_mode = "none";
defparam \pll_reset~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_H2
cycloneii_io \ref_clock~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\ref_clock~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(ref_clock));
// synopsys translate_off
defparam \ref_clock~I .input_async_reset = "none";
defparam \ref_clock~I .input_power_up = "low";
defparam \ref_clock~I .input_register_mode = "none";
defparam \ref_clock~I .input_sync_reset = "none";
defparam \ref_clock~I .oe_async_reset = "none";
defparam \ref_clock~I .oe_power_up = "low";
defparam \ref_clock~I .oe_register_mode = "none";
defparam \ref_clock~I .oe_sync_reset = "none";
defparam \ref_clock~I .operation_mode = "input";
defparam \ref_clock~I .output_async_reset = "none";
defparam \ref_clock~I .output_power_up = "low";
defparam \ref_clock~I .output_register_mode = "none";
defparam \ref_clock~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_E1
cycloneii_io \inst|altlvds_rx_component|auto_generated|ddio_in_posa_3~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(\inst2|altpll_component|_clk0~clkctrl_outclk ),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(\inst|altlvds_rx_component|auto_generated|wire_ddio_in_posa_regout [3]),
	.differentialout(\inst|altlvds_rx_component|auto_generated|wire_ddio_in_nega_differentialin [3]),
	.linkout(),
	.padio(rx_in[3]));
// synopsys translate_off
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_3~I .input_async_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_3~I .input_power_up = "low";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_3~I .input_register_mode = "register";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_3~I .input_sync_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_3~I .oe_async_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_3~I .oe_power_up = "low";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_3~I .oe_register_mode = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_3~I .oe_sync_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_3~I .operation_mode = "input";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_3~I .output_async_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_3~I .output_power_up = "low";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_3~I .output_register_mode = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_3~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_K2
cycloneii_io \inst|altlvds_rx_component|auto_generated|ddio_in_posa_2~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(\inst2|altpll_component|_clk0~clkctrl_outclk ),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(\inst|altlvds_rx_component|auto_generated|wire_ddio_in_posa_regout [2]),
	.differentialout(\inst|altlvds_rx_component|auto_generated|wire_ddio_in_nega_differentialin [2]),
	.linkout(),
	.padio(rx_in[2]));
// synopsys translate_off
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_2~I .input_async_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_2~I .input_power_up = "low";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_2~I .input_register_mode = "register";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_2~I .input_sync_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_2~I .oe_async_reset = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_2~I .oe_power_up = "low";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_2~I .oe_register_mode = "none";
defparam \inst|altlvds_rx_component|auto_generated|ddio_in_posa_2~I .oe_sync_reset = "none";