cii_altlvds_extpll.vt

CPLD/FPGA常用模块与综合系统设计实例光盘程序

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors  
// are exported from a vector file in the Quartus Waveform Editor and apply to  
// the top level entity of the current Quartus project .The user can use this   
// testbench to simulate his design using a third-party simulation tool .       
// *****************************************************************************
// Generated on "09/05/2007 21:32:37"
                                                                                
// Verilog Test Bench (with test vectors) for design :                          cii_altlvds_extpll
// 
// Simulation tool : 3rd Party
// 

`timescale 1 ps/ 1 ps
module cii_altlvds_extpll_vlg_vec_tst();
// constants                                           
// general purpose registers
reg pll_reset;
reg ref_clock;
reg [3:0] rx_in;
reg [31:0] tx_parallel_data;
// wires                                               
wire pll_lock;
wire [31:0] rx_parallel_out;
wire slow_clock;
wire [3:0] tx_out;

// assign statements (if any)                          
cii_altlvds_extpll i1 (
// port map - connection between master ports and signals/registers   
	.pll_lock(pll_lock),
	.pll_reset(pll_reset),
	.ref_clock(ref_clock),
	.rx_in(rx_in),
	.rx_parallel_out(rx_parallel_out),
	.slow_clock(slow_clock),
	.tx_out(tx_out),
	.tx_parallel_data(tx_parallel_data)
);
initial 
begin 
#1000000 $stop;
end 

// pll_reset
initial
begin
	pll_reset = 1'b0;
end 

// ref_clock
initial
begin
	repeat(75)
	begin
		ref_clock = 1'b0;
		ref_clock = #6667 1'b1;
		# 6666;
	end
	ref_clock = 1'b0;
end 
// rx_in[ 3 ]
initial
begin
	rx_in[3] = 1'b0;
	rx_in[3] = #81585 1'b1;
	rx_in[3] = #1700 1'b0;
end 
// rx_in[ 2 ]
initial
begin
	rx_in[2] = 1'b0;
	rx_in[2] = #81635 1'b1;
	rx_in[2] = #3300 1'b0;
end 
// rx_in[ 1 ]
initial
begin
	rx_in[1] = 1'b0;
	rx_in[1] = #83285 1'b1;
	rx_in[1] = #1750 1'b0;
end 
// rx_in[ 0 ]
initial
begin
	rx_in[0] = 1'b0;
	rx_in[0] = #84985 1'b1;
	rx_in[0] = #1649 1'b0;
end 
// tx_parallel_data[ 31 ]
initial
begin
	tx_parallel_data[31] = 1'b0;
end 
// tx_parallel_data[ 30 ]
initial
begin
	tx_parallel_data[30] = 1'b0;
end 
// tx_parallel_data[ 29 ]
initial
begin
	tx_parallel_data[29] = 1'b0;
end 
// tx_parallel_data[ 28 ]
initial
begin
	tx_parallel_data[28] = 1'b0;
end 
// tx_parallel_data[ 27 ]
initial
begin
	tx_parallel_data[27] = 1'b0;
end 
// tx_parallel_data[ 26 ]
initial
begin
	tx_parallel_data[26] = 1'b0;
	tx_parallel_data[26] = #110476 1'b1;
	tx_parallel_data[26] = #13097 1'b0;
end 
// tx_parallel_data[ 25 ]
initial
begin
	tx_parallel_data[25] = 1'b0;
end 
// tx_parallel_data[ 24 ]
initial
begin
	tx_parallel_data[24] = 1'b0;
end 
// tx_parallel_data[ 23 ]
initial
begin
	tx_parallel_data[23] = 1'b0;
end 
// tx_parallel_data[ 22 ]
initial
begin
	tx_parallel_data[22] = 1'b0;
end 
// tx_parallel_data[ 21 ]
initial
begin
	tx_parallel_data[21] = 1'b0;
end 
// tx_parallel_data[ 20 ]
initial
begin
	tx_parallel_data[20] = 1'b0;
end 
// tx_parallel_data[ 19 ]
initial
begin
	tx_parallel_data[19] = 1'b0;
end 
// tx_parallel_data[ 18 ]
initial
begin
	tx_parallel_data[18] = 1'b0;
end 
// tx_parallel_data[ 17 ]
initial
begin
	tx_parallel_data[17] = 1'b0;
	tx_parallel_data[17] = #110426 1'b1;
	tx_parallel_data[17] = #13197 1'b0;
end 
// tx_parallel_data[ 16 ]
initial
begin
	tx_parallel_data[16] = 1'b0;
	tx_parallel_data[16] = #110426 1'b1;
	tx_parallel_data[16] = #13197 1'b0;
end 
// tx_parallel_data[ 15 ]
initial
begin
	tx_parallel_data[15] = 1'b0;
end 
// tx_parallel_data[ 14 ]
initial
begin
	tx_parallel_data[14] = 1'b0;
end 
// tx_parallel_data[ 13 ]
initial
begin
	tx_parallel_data[13] = 1'b0;
end 
// tx_parallel_data[ 12 ]
initial
begin
	tx_parallel_data[12] = 1'b0;
end 
// tx_parallel_data[ 11 ]
initial
begin
	tx_parallel_data[11] = 1'b0;
end 
// tx_parallel_data[ 10 ]
initial
begin
	tx_parallel_data[10] = 1'b0;
end 
// tx_parallel_data[ 9 ]
initial
begin
	tx_parallel_data[9] = 1'b0;
	tx_parallel_data[9] = #110376 1'b1;
	tx_parallel_data[9] = #13297 1'b0;
end 
// tx_parallel_data[ 8 ]
initial
begin
	tx_parallel_data[8] = 1'b0;
end 
// tx_parallel_data[ 7 ]
initial
begin
	tx_parallel_data[7] = 1'b0;
end 
// tx_parallel_data[ 6 ]
initial
begin
	tx_parallel_data[6] = 1'b0;
end 
// tx_parallel_data[ 5 ]
initial
begin
	tx_parallel_data[5] = 1'b0;
end 
// tx_parallel_data[ 4 ]
initial
begin
	tx_parallel_data[4] = 1'b0;
end 
// tx_parallel_data[ 3 ]
initial
begin
	tx_parallel_data[3] = 1'b0;
end 
// tx_parallel_data[ 2 ]
initial
begin
	tx_parallel_data[2] = 1'b0;
end 
// tx_parallel_data[ 1 ]
initial
begin
	tx_parallel_data[1] = 1'b0;
end 
// tx_parallel_data[ 0 ]
initial
begin
	tx_parallel_data[0] = 1'b0;
	tx_parallel_data[0] = #110426 1'b1;
	tx_parallel_data[0] = #13147 1'b0;
end 
endmodule