altlvds_stratixii.vt

CPLD/FPGA常用模块与综合系统设计实例光盘程序

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors  
// are exported from a vector file in the Quartus Waveform Editor and apply to  
// the top level entity of the current Quartus project .The user can use this   
// testbench to simulate his design using a third-party simulation tool .       
// *****************************************************************************
// Generated on "09/04/2007 22:51:33"
                                                                                
// Verilog Test Bench (with test vectors) for design :                          altlvds_stratixII
// 
// Simulation tool : 3rd Party
// 

`timescale 1 ps/ 1 ps
module altlvds_stratixII_vlg_vec_tst();
// constants                                           
// general purpose registers
reg CLK_IN_500MHZ;
reg PLL_ARESET;
reg PLL_ENABLE;
reg [7:0] RX_CDA_RST;
reg [7:0] RX_CH_DATA_ALIGN;
reg [7:0] RX_DPLL_EN;
reg [7:0] RX_DPLL_HOLD;
reg [7:0] RX_FIFO_RST;
reg [7:0] RX_IN;
reg [7:0] RX_RESET;
// wires                                               
wire [7:0] CDA_MAX;
wire PLL_LOCK;
wire [7:0] RX_DPA_LOCKED;
wire RX_OUTCLOCK;
wire TX_CORECLOCK;
wire [7:0] TX_OUT;
wire TX_OUTCLOCK;

// assign statements (if any)                          
altlvds_stratixII i1 (
// port map - connection between master ports and signals/registers   
	.CDA_MAX(CDA_MAX),
	.CLK_IN_500MHZ(CLK_IN_500MHZ),
	.PLL_ARESET(PLL_ARESET),
	.PLL_ENABLE(PLL_ENABLE),
	.PLL_LOCK(PLL_LOCK),
	.RX_CDA_RST(RX_CDA_RST),
	.RX_CH_DATA_ALIGN(RX_CH_DATA_ALIGN),
	.RX_DPA_LOCKED(RX_DPA_LOCKED),
	.RX_DPLL_EN(RX_DPLL_EN),
	.RX_DPLL_HOLD(RX_DPLL_HOLD),
	.RX_FIFO_RST(RX_FIFO_RST),
	.RX_IN(RX_IN),
	.RX_OUTCLOCK(RX_OUTCLOCK),
	.RX_RESET(RX_RESET),
	.TX_CORECLOCK(TX_CORECLOCK),
	.TX_OUT(TX_OUT),
	.TX_OUTCLOCK(TX_OUTCLOCK)
);
initial 
begin 
#2000000 $stop;
end 
// RX_CDA_RST[ 7 ]
initial
begin
	RX_CDA_RST[7] = 1'b0;
	RX_CDA_RST[7] = #49 1'b1;
	RX_CDA_RST[7] = #49910 1'b0;
end 
// RX_CDA_RST[ 6 ]
initial
begin
	RX_CDA_RST[6] = 1'b0;
	RX_CDA_RST[6] = #49 1'b1;
	RX_CDA_RST[6] = #49910 1'b0;
end 
// RX_CDA_RST[ 5 ]
initial
begin
	RX_CDA_RST[5] = 1'b0;
	RX_CDA_RST[5] = #49 1'b1;
	RX_CDA_RST[5] = #49910 1'b0;
end 
// RX_CDA_RST[ 4 ]
initial
begin
	RX_CDA_RST[4] = 1'b0;
	RX_CDA_RST[4] = #49 1'b1;
	RX_CDA_RST[4] = #49910 1'b0;
end 
// RX_CDA_RST[ 3 ]
initial
begin
	RX_CDA_RST[3] = 1'b0;
	RX_CDA_RST[3] = #49 1'b1;
	RX_CDA_RST[3] = #49910 1'b0;
end 
// RX_CDA_RST[ 2 ]
initial
begin
	RX_CDA_RST[2] = 1'b0;
	RX_CDA_RST[2] = #49 1'b1;
	RX_CDA_RST[2] = #49910 1'b0;
end 
// RX_CDA_RST[ 1 ]
initial
begin
	RX_CDA_RST[1] = 1'b0;
	RX_CDA_RST[1] = #49 1'b1;
	RX_CDA_RST[1] = #49910 1'b0;
end 
// RX_CDA_RST[ 0 ]
initial
begin
	RX_CDA_RST[0] = 1'b0;
	RX_CDA_RST[0] = #49 1'b1;
	RX_CDA_RST[0] = #49910 1'b0;
end 
// RX_RESET[ 7 ]
initial
begin
	RX_RESET[7] = 1'b0;
	RX_RESET[7] = #49 1'b1;
	RX_RESET[7] = #49910 1'b0;
end 
// RX_RESET[ 6 ]
initial
begin
	RX_RESET[6] = 1'b0;
	RX_RESET[6] = #49 1'b1;
	RX_RESET[6] = #49910 1'b0;
end 
// RX_RESET[ 5 ]
initial
begin
	RX_RESET[5] = 1'b0;
	RX_RESET[5] = #49 1'b1;
	RX_RESET[5] = #49910 1'b0;
end 
// RX_RESET[ 4 ]
initial
begin
	RX_RESET[4] = 1'b0;
	RX_RESET[4] = #49 1'b1;
	RX_RESET[4] = #49910 1'b0;
end 
// RX_RESET[ 3 ]
initial
begin
	RX_RESET[3] = 1'b0;
	RX_RESET[3] = #49 1'b1;
	RX_RESET[3] = #49910 1'b0;
end 
// RX_RESET[ 2 ]
initial
begin
	RX_RESET[2] = 1'b0;
	RX_RESET[2] = #49 1'b1;
	RX_RESET[2] = #49910 1'b0;
end 
// RX_RESET[ 1 ]
initial
begin
	RX_RESET[1] = 1'b0;
	RX_RESET[1] = #49 1'b1;
	RX_RESET[1] = #49910 1'b0;
end 
// RX_RESET[ 0 ]
initial
begin
	RX_RESET[0] = 1'b0;
	RX_RESET[0] = #49 1'b1;
	RX_RESET[0] = #49910 1'b0;
end 
// RX_FIFO_RST[ 7 ]
initial
begin
	RX_FIFO_RST[7] = 1'b0;
	RX_FIFO_RST[7] = #49 1'b1;
	RX_FIFO_RST[7] = #49910 1'b0;
end 
// RX_FIFO_RST[ 6 ]
initial
begin
	RX_FIFO_RST[6] = 1'b0;
	RX_FIFO_RST[6] = #49 1'b1;
	RX_FIFO_RST[6] = #49910 1'b0;
end 
// RX_FIFO_RST[ 5 ]
initial
begin
	RX_FIFO_RST[5] = 1'b0;
	RX_FIFO_RST[5] = #49 1'b1;
	RX_FIFO_RST[5] = #49910 1'b0;
end 
// RX_FIFO_RST[ 4 ]
initial
begin
	RX_FIFO_RST[4] = 1'b0;
	RX_FIFO_RST[4] = #49 1'b1;
	RX_FIFO_RST[4] = #49910 1'b0;
end 
// RX_FIFO_RST[ 3 ]
initial
begin
	RX_FIFO_RST[3] = 1'b0;
	RX_FIFO_RST[3] = #49 1'b1;
	RX_FIFO_RST[3] = #49910 1'b0;
end 
// RX_FIFO_RST[ 2 ]
initial
begin
	RX_FIFO_RST[2] = 1'b0;
	RX_FIFO_RST[2] = #49 1'b1;
	RX_FIFO_RST[2] = #49910 1'b0;
end 
// RX_FIFO_RST[ 1 ]
initial
begin
	RX_FIFO_RST[1] = 1'b0;
	RX_FIFO_RST[1] = #49 1'b1;
	RX_FIFO_RST[1] = #49910 1'b0;
end 
// RX_FIFO_RST[ 0 ]
initial
begin
	RX_FIFO_RST[0] = 1'b0;
	RX_FIFO_RST[0] = #49 1'b1;
	RX_FIFO_RST[0] = #49910 1'b0;
end 
// RX_CH_DATA_ALIGN[ 7 ]
initial
begin
	RX_CH_DATA_ALIGN[7] = 1'b0;
end 
// RX_CH_DATA_ALIGN[ 6 ]
initial
begin
	RX_CH_DATA_ALIGN[6] = 1'b0;
end 
// RX_CH_DATA_ALIGN[ 5 ]
initial
begin
	RX_CH_DATA_ALIGN[5] = 1'b0;
end 
// RX_CH_DATA_ALIGN[ 4 ]
initial
begin
	RX_CH_DATA_ALIGN[4] = 1'b0;
end 
// RX_CH_DATA_ALIGN[ 3 ]
initial
begin
	RX_CH_DATA_ALIGN[3] = 1'b0;
end 
// RX_CH_DATA_ALIGN[ 2 ]
initial
begin
	RX_CH_DATA_ALIGN[2] = 1'b0;
end 
// RX_CH_DATA_ALIGN[ 1 ]
initial
begin
	RX_CH_DATA_ALIGN[1] = 1'b0;
end 
// RX_CH_DATA_ALIGN[ 0 ]
initial
begin
	RX_CH_DATA_ALIGN[0] = 1'b0;
end 
// RX_DPLL_EN[ 7 ]
initial
begin
	RX_DPLL_EN[7] = 1'b0;
end 
// RX_DPLL_EN[ 6 ]
initial
begin
	RX_DPLL_EN[6] = 1'b0;
end 
// RX_DPLL_EN[ 5 ]
initial
begin
	RX_DPLL_EN[5] = 1'b0;
end 
// RX_DPLL_EN[ 4 ]
initial
begin
	RX_DPLL_EN[4] = 1'b0;
end 
// RX_DPLL_EN[ 3 ]
initial
begin
	RX_DPLL_EN[3] = 1'b0;
end 
// RX_DPLL_EN[ 2 ]
initial
begin
	RX_DPLL_EN[2] = 1'b0;
end 
// RX_DPLL_EN[ 1 ]
initial
begin
	RX_DPLL_EN[1] = 1'b0;
end 
// RX_DPLL_EN[ 0 ]
initial
begin
	RX_DPLL_EN[0] = 1'b0;
end 
// RX_DPLL_HOLD[ 7 ]
initial
begin
	RX_DPLL_HOLD[7] = 1'b0;
end 
// RX_DPLL_HOLD[ 6 ]
initial
begin
	RX_DPLL_HOLD[6] = 1'b0;
end 
// RX_DPLL_HOLD[ 5 ]
initial
begin
	RX_DPLL_HOLD[5] = 1'b0;
end 
// RX_DPLL_HOLD[ 4 ]
initial
begin
	RX_DPLL_HOLD[4] = 1'b0;
end 
// RX_DPLL_HOLD[ 3 ]
initial
begin
	RX_DPLL_HOLD[3] = 1'b0;
end 
// RX_DPLL_HOLD[ 2 ]
initial
begin
	RX_DPLL_HOLD[2] = 1'b0;
end 
// RX_DPLL_HOLD[ 1 ]
initial
begin
	RX_DPLL_HOLD[1] = 1'b0;
end 
// RX_DPLL_HOLD[ 0 ]
initial
begin
	RX_DPLL_HOLD[0] = 1'b0;
end 

// PLL_ARESET
initial
begin
	PLL_ARESET = 1'b0;
	PLL_ARESET = #50 1'b1;
	PLL_ARESET = #14900 1'b0;
end 

// PLL_ENABLE
initial
begin
	PLL_ENABLE = 1'b1;
	PLL_ENABLE = #50 1'b0;
	PLL_ENABLE = #19700 1'b1;
end 

// CLK_IN_500MHZ
always
begin
	CLK_IN_500MHZ = 1'b0;
	CLK_IN_500MHZ = #1000 1'b1;
	#1000;
end 
// RX_IN[ 7 ]
initial
begin
	RX_IN[7] = 1'b0;
	RX_IN[7] = #49 1'b1;
	RX_IN[7] = #255951 1'b0;
	RX_IN[7] = #128000 1'b1;
	# 128000;
	repeat(5)
	begin
		RX_IN[7] = 1'b0;
		RX_IN[7] = #128000 1'b1;
		# 128000;
	end
	RX_IN[7] = 1'b0;
	RX_IN[7] = #128000 1'b1;
end 
// RX_IN[ 6 ]
initial
begin
	RX_IN[6] = 1'b0;
	RX_IN[6] = #49 1'b1;
	RX_IN[6] = #255951 1'b0;
	RX_IN[6] = #64000 1'b1;
	# 64000;
	repeat(12)
	begin
		RX_IN[6] = 1'b0;
		RX_IN[6] = #64000 1'b1;
		# 64000;
	end
	RX_IN[6] = 1'b0;
	RX_IN[6] = #64000 1'b1;
end 
// RX_IN[ 5 ]
initial
begin
	RX_IN[5] = 1'b0;
	RX_IN[5] = #49 1'b1;
	RX_IN[5] = #255951 1'b0;
	RX_IN[5] = #32000 1'b1;
	# 32000;
	repeat(26)
	begin
		RX_IN[5] = 1'b0;
		RX_IN[5] = #32000 1'b1;
		# 32000;
	end
	RX_IN[5] = 1'b0;
end 
// RX_IN[ 4 ]
initial
begin
	RX_IN[4] = 1'b0;
	RX_IN[4] = #49 1'b1;
	RX_IN[4] = #255951 1'b0;
	RX_IN[4] = #16000 1'b1;
	# 16000;
	repeat(53)
	begin
		RX_IN[4] = 1'b0;
		RX_IN[4] = #16000 1'b1;
		# 16000;
	end
	RX_IN[4] = 1'b0;
end 
// RX_IN[ 3 ]
initial
begin
	RX_IN[3] = 1'b0;
	RX_IN[3] = #49 1'b1;
	RX_IN[3] = #255951 1'b0;
	RX_IN[3] = #8000 1'b1;
	# 8000;
	repeat(108)
	begin
		RX_IN[3] = 1'b0;
		RX_IN[3] = #8000 1'b1;
		# 8000;
	end
end 
// RX_IN[ 2 ]
initial
begin
	RX_IN[2] = 1'b0;
	RX_IN[2] = #49 1'b1;
	RX_IN[2] = #255951 1'b0;
	RX_IN[2] = #4000 1'b1;
	# 4000;
	repeat(217)
	begin
		RX_IN[2] = 1'b0;
		RX_IN[2] = #4000 1'b1;
		# 4000;
	end
end 
// RX_IN[ 1 ]
initial
begin
	RX_IN[1] = 1'b0;
	RX_IN[1] = #49 1'b1;
	RX_IN[1] = #255951 1'b0;
	RX_IN[1] = #2000 1'b1;
	# 2000;
	repeat(435)
	begin
		RX_IN[1] = 1'b0;
		RX_IN[1] = #2000 1'b1;
		# 2000;
	end
end 
// RX_IN[ 0 ]
initial
begin
	RX_IN[0] = 1'b0;
	RX_IN[0] = #49 1'b1;
	RX_IN[0] = #255951 1'b0;
	RX_IN[0] = #1000 1'b1;
	# 1000;
	repeat(871)
	begin
		RX_IN[0] = 1'b0;
		RX_IN[0] = #1000 1'b1;
		# 1000;
	end
end 
endmodule