altlvds_ex1_msim.do

CPLD/FPGA常用模块与综合系统设计实例光盘程序

vlib work
vmap work work
vlib my_atom
vmap my_atom my_atom
vlog -work work altlvds_stratixII.vt altlvds_stratixII.vo
vlog -work my_atom stratixii_atoms.v
vsim -L my_atom -t ps work.altlvds_stratixII_vlg_vec_tst 
view wave
add wave -binary /altlvds_stratixII_vlg_vec_tst/*RX_CDA_RST
add wave -binary /altlvds_stratixII_vlg_vec_tst/*RX_RESET
add wave -binary /altlvds_stratixII_vlg_vec_tst/*RX_FIFO_RST
add wave -binary /altlvds_stratixII_vlg_vec_tst/*RX_CH_DATA_ALIGN
add wave -binary /altlvds_stratixII_vlg_vec_tst/*RX_DPLL_EN
add wave -binary /altlvds_stratixII_vlg_vec_tst/*RX_DPLL_HOLD
add wave -binary /altlvds_stratixII_vlg_vec_tst/*PLL_ARESET
add wave -binary /altlvds_stratixII_vlg_vec_tst/*PLL_ENABLE
add wave -binary /altlvds_stratixII_vlg_vec_tst/*CLK_IN_500MHZ
add wave -binary /altlvds_stratixII_vlg_vec_tst/*RX_IN
add wave -binary /altlvds_stratixII_vlg_vec_tst/*RX_OUTCLOCK
add wave -binary /altlvds_stratixII_vlg_vec_tst/*TX_OUT
add wave -binary /altlvds_stratixII_vlg_vec_tst/*TX_OUTCLOCK
add wave -binary /altlvds_stratixII_vlg_vec_tst/*TX_CORECLOCK
add wave -binary /altlvds_stratixII_vlg_vec_tst/*CDA_MAX
add wave -binary /altlvds_stratixII_vlg_vec_tst/*PLL_LOCK
add wave -binary /altlvds_stratixII_vlg_vec_tst/*RX_DPA_LOCKED
run 2us