yequ.vhd

基于VHDL的乐曲演奏硬件电路,基于AT的FPGA,由Quartus2编译通过

width=4;
depth=256;
address_radix=dec;
data_radix=dec;
content begin
 00:3; 
 01:3; 
 02:3; 
 03:3; 
 04:5; 
 05:5; 
 06:5;
  07:6; 
 08:8; 
 09:8;
 10:8; 
 11:9; 
 12:6;
  13:8; 
 14:5; 
 15:5; 
 16:12;
 17:12; 
18:12; 
19:15;
 20:13;
 21:12; 
22:10; 
23:12; 
24:9;  
25:9;  
26:9;  
27:9;  
28:9;  
29:9;
 30:9; 
 31:0;  
32:9; 

 33:9;
  34:9; 
 35:10; 
36:7; 
 37:7;
  38:6;
  39:6;
 40:5; 
 41:5; 
 42:5;  
43:6;  
44:8;  
45:8; 
 46:9; 
 47:9;  
48:3;  
49:3;
 50:8; 
 51:8; 
 52:6; 
 53:5; 
 54:6; 
 55:8; 
 56:5; 
 57:5; 
 58:5; 
 59:5;
 60:5; 
 61:5; 
 62:5; 
 63:5; 
 64:10;
 65:10;
 66:10;
 67:12;
 68:7; 
 69:7;
 70:9; 
 71:9;  
72:6;  
73:8;  
74:5;  
75:5;  
76:5;  
77:5;  
78:5;  
79:5;
 80:3; 
 81:5; 
 82:3; 
 83:3; 
 84:5; 
 85:6; 
 86:7; 
 87:9; 
 88:6; 
 89:6;
 90:6; 
 91:6; 
 92:6; 
 93:6; 
 94:5; 
 95:6; 
 96:8;
97:8; 
 98:8;  
99:9;
100:12;
101:12;
102:12;
103:10;
104:9; 
105:9; 
106:10;
107:9; 
108:8; 
109:8;
110:6; 
111:5;
 112:3; 
113:3;
 114:3;
 115:3;
 116:8;
 117:8:
 118:8;
 119:8;
120:6; 
121:8; 
122:6; 
123:5; 
124:3; 
125:5; 
126:6; 
127:8; 
128:5;
 129:5;
130:5; 
131:5; 
132:5; 
133:5; 
134:5; 
135:5; 
136:0; 
137:0; 
138:0;
end;