songer.vhd

基于VHDL的乐曲演奏硬件电路,基于AT的FPGA,由Quartus2编译通过

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL ; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL ; 
LIBRARY altera; 
USE altera.maxplus2.ALL; 

ENTITY songer IS
PORT(CLK12MHZ:IN STD_LOGIC;
     CLK8HZ:  IN STD_LOGIC;
     CODE1:   OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
     HIGH1:   OUT STD_LOGIC ;
     SPKOUT:  OUT STD_LOGIC);
END;

ARCHITECTURE one OF songer IS
  COMPONENT NoteTabs
    PORT  (clk:IN STD_LOGIC;
            ToneIndex: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
  END COMPONENT;
  
  COMPONENT ToneTaba
    PORT (Index:STD_LOGIC_VECTOR(3 DOWNTO 0);
          CODE :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
          HIGH: OUT STD_LOGIC;
          Tone: OUT STD_LOGIC_VECTOR(10 DOWNTO 0));
  END COMPONENT;

  COMPONENT Speakera
   PORT (clk: IN STD_LOGIC;
         Tone:IN STD_LOGIC_VECTOR(10 DOWNTO 0);
         Spks:OUT STD_LOGIC);
  END COMPONENT;

SIGNAL Tone :STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL ToneIndex:STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN
U1:NoteTabs PORT MAP (clk=>CLK8HZ,ToneIndex=>ToneIndex);
U2:ToneTaba PORT MAP (Index=>ToneIndex,Tone=>Tone,CODE=>CODE1,HIGH=>HIGH1);
U3:Speakera PORT MAP (clk=>CLK12MHZ,Tone=>Tone,Spks=>SPKOUT);
END ARCHITECTURE one;