📄 speakera.rpt
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Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\vhdl\songer-03_24\speakera.rpt
speakera
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - A 23 DFFE 0 2 1 0 :13
- 1 - A 17 DFFE 0 1 0 2 FullSpks (:16)
- 6 - A 17 DFFE + 0 4 0 1 Count43 (:18)
- 5 - A 17 DFFE + 0 3 0 2 Count42 (:19)
- 4 - A 17 DFFE + 0 2 0 2 Count41 (:20)
- 3 - A 17 DFFE + 0 1 0 3 Count40 (:21)
- 2 - A 17 OR2 ! 0 2 0 5 :27
- 1 - A 23 DFFE 0 1 0 1 Count2 (:252)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\vhdl\songer-03_24\speakera.rpt
speakera
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\vhdl\songer-03_24\speakera.rpt
speakera
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 5 :27
INPUT 4 clk
DFF 2 FullSpks
Device-Specific Information: d:\vhdl\songer-03_24\speakera.rpt
speakera
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 5 :27
Device-Specific Information: d:\vhdl\songer-03_24\speakera.rpt
speakera
** EQUATIONS **
clk : INPUT;
-- Node name is ':252' = 'Count2'
-- Equation name is 'Count2', location is LC1_A23, type is buried.
Count2 = DFFE(!Count2, FullSpks, VCC, VCC, VCC);
-- Node name is ':21' = 'Count40'
-- Equation name is 'Count40', location is LC3_A17, type is buried.
Count40 = DFFE(!Count40, GLOBAL( clk), !_LC2_A17, VCC, VCC);
-- Node name is ':20' = 'Count41'
-- Equation name is 'Count41', location is LC4_A17, type is buried.
Count41 = DFFE( _EQ001, GLOBAL( clk), !_LC2_A17, VCC, VCC);
_EQ001 = Count40 & !Count41
# !Count40 & Count41;
-- Node name is ':19' = 'Count42'
-- Equation name is 'Count42', location is LC5_A17, type is buried.
Count42 = DFFE( _EQ002, GLOBAL( clk), !_LC2_A17, VCC, VCC);
_EQ002 = !Count40 & Count42
# !Count41 & Count42
# Count40 & Count41 & !Count42;
-- Node name is ':18' = 'Count43'
-- Equation name is 'Count43', location is LC6_A17, type is buried.
Count43 = DFFE( _EQ003, GLOBAL( clk), !_LC2_A17, VCC, VCC);
_EQ003 = !Count42 & Count43
# !Count40 & Count43
# !Count41 & Count43
# Count40 & Count41 & Count42 & !Count43;
-- Node name is ':16' = 'FullSpks'
-- Equation name is 'FullSpks', location is LC1_A17, type is buried.
FullSpks = DFFE( VCC, _LC2_A17, VCC, VCC, VCC);
-- Node name is 'SpkS'
-- Equation name is 'SpkS', type is output
SpkS = _LC5_A23;
-- Node name is ':13'
-- Equation name is '_LC5_A23', type is buried
_LC5_A23 = DFFE(!Count2, FullSpks, VCC, VCC, VCC);
-- Node name is ':27'
-- Equation name is '_LC2_A17', type is buried
!_LC2_A17 = _LC2_A17~NOT;
_LC2_A17~NOT = LCELL( _EQ004);
_EQ004 = !Count42
# !Count43;
Project Information d:\vhdl\songer-03_24\speakera.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,191K
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