tonetaba.rpt

基于VHDL的乐曲演奏硬件电路,基于AT的FPGA,由Quartus2编译通过

         #  _LC5_A20;

-- Node name is ':1019' 
-- Equation name is '_LC2_A23', type is buried 
_LC2_A23 = LCELL( _EQ031);
  _EQ031 =  _LC1_A23 &  _LC2_A13 & !_LC8_A20
         #  _LC6_A20;

-- Node name is ':1045' 
-- Equation name is '_LC7_A15', type is buried 
_LC7_A15 = LCELL( _EQ032);
  _EQ032 = !_LC4_A18 &  _LC6_A15 &  _LC7_A18
         #  _LC5_A18 &  _LC7_A18;

-- Node name is '~1057~1' 
-- Equation name is '~1057~1', location is LC4_A22, type is buried.
-- synthesized logic cell 
_LC4_A22 = LCELL( _EQ033);
  _EQ033 = !_LC4_A20 & !_LC5_A20;

-- Node name is ':1057' 
-- Equation name is '_LC8_A15', type is buried 
_LC8_A15 = LCELL( _EQ034);
  _EQ034 = !_LC1_A24 &  _LC4_A22 &  _LC7_A15
         # !_LC1_A24 &  _LC2_A24 &  _LC4_A22;

-- Node name is ':1061' 
-- Equation name is '_LC6_A15', type is buried 
_LC6_A15 = LCELL( _EQ035);
  _EQ035 =  _LC8_A15 & !_LC8_A20
         #  _LC7_A20 & !_LC8_A20
         #  _LC6_A20;

-- Node name is ':1087' 
-- Equation name is '_LC3_A13', type is buried 
_LC3_A13 = LCELL( _EQ036);
  _EQ036 = !_LC2_A20 &  _LC6_A13 & !_LC6_A18
         #  _LC1_A20 & !_LC2_A20;

-- Node name is ':1103' 
-- Equation name is '_LC6_A13', type is buried 
_LC6_A13 = LCELL( _EQ037);
  _EQ037 =  _LC1_A13 &  _LC2_A22
         #  _LC1_A13 &  _LC3_A13
         #  _LC6_A20;

-- Node name is ':1118' 
-- Equation name is '_LC3_A16', type is buried 
_LC3_A16 = LCELL( _EQ038);
  _EQ038 = !_LC2_A18 &  _LC4_A15
         #  _LC3_A18
         #  _LC3_A20;

-- Node name is ':1135' 
-- Equation name is '_LC4_A16', type is buried 
_LC4_A16 = LCELL( _EQ039);
  _EQ039 =  _LC1_A16 & !_LC1_A24 &  _LC3_A16
         # !_LC1_A24 &  _LC2_A24;

-- Node name is ':1145' 
-- Equation name is '_LC4_A15', type is buried 
_LC4_A15 = LCELL( _EQ040);
  _EQ040 =  _LC4_A16 & !_LC7_A20
         # !_LC4_A22 & !_LC7_A20
         #  _LC3_A22;

-- Node name is ':1168' 
-- Equation name is '_LC2_A15', type is buried 
_LC2_A15 = LCELL( _EQ041);
  _EQ041 = !_LC1_A20 &  _LC3_A18
         # !_LC1_A20 &  _LC3_A15 & !_LC4_A18;

-- Node name is ':1172' 
-- Equation name is '_LC5_A15', type is buried 
_LC5_A15 = LCELL( _EQ042);
  _EQ042 =  _LC2_A15 & !_LC2_A24
         #  _LC2_A20 & !_LC2_A24
         #  _LC1_A24;

-- Node name is ':1187' 
-- Equation name is '_LC3_A15', type is buried 
_LC3_A15 = LCELL( _EQ043);
  _EQ043 =  _LC1_A13 &  _LC4_A22 &  _LC5_A15
         #  _LC6_A20;

-- Node name is '~1219~1' 
-- Equation name is '~1219~1', location is LC7_A18, type is buried.
-- synthesized logic cell 
_LC7_A18 = LCELL( _EQ044);
  _EQ044 =  _LC1_A16 & !_LC1_A18;

-- Node name is ':1219' 
-- Equation name is '_LC1_A17', type is buried 
_LC1_A17 = LCELL( _EQ045);
  _EQ045 = !_LC1_A15 &  _LC4_A24 &  _LC7_A17;

-- Node name is '~1228~1' 
-- Equation name is '~1228~1', location is LC2_A13, type is buried.
-- synthesized logic cell 
_LC2_A13 = LCELL( _EQ046);
  _EQ046 = !_LC4_A20 & !_LC7_A20;

-- Node name is '~1229~1' 
-- Equation name is '~1229~1', location is LC3_A22, type is buried.
-- synthesized logic cell 
_LC3_A22 = LCELL( _EQ047);
  _EQ047 =  _LC8_A20
         #  _LC6_A20;

-- Node name is ':1229' 
-- Equation name is '_LC7_A17', type is buried 
_LC7_A17 = LCELL( _EQ048);
  _EQ048 =  _LC3_A22
         #  _LC2_A13 &  _LC5_A20
         #  _LC1_A17 &  _LC2_A13;

-- Node name is ':1271' 
-- Equation name is '_LC5_A23', type is buried 
_LC5_A23 = LCELL( _EQ049);
  _EQ049 = !_LC1_A15 & !_LC2_A22 &  _LC5_A23 &  _LC7_A23;

-- Node name is '~1273~1' 
-- Equation name is '~1273~1', location is LC4_A24, type is buried.
-- synthesized logic cell 
_LC4_A24 = LCELL( _EQ050);
  _EQ050 = !_LC1_A24 & !_LC2_A24;

-- Node name is '~1273~2' 
-- Equation name is '~1273~2', location is LC3_A23, type is buried.
-- synthesized logic cell 
!_LC3_A23 = _LC3_A23~NOT;
_LC3_A23~NOT = LCELL( _EQ051);
  _EQ051 =  _LC2_A22
         #  _LC1_A15;

-- Node name is '~1273~3' 
-- Equation name is '~1273~3', location is LC7_A23, type is buried.
-- synthesized logic cell 
_LC7_A23 = LCELL( _EQ052);
  _EQ052 = !_LC6_A20 & !_LC7_A20 & !_LC8_A20;

-- Node name is ':1283' 
-- Equation name is '_LC6_A22', type is buried 
_LC6_A22 = LCELL( _EQ053);
  _EQ053 = !_LC2_A18 &  _LC8_A22
         #  _LC3_A20
         #  _LC5_A18;

-- Node name is '~1297~1' 
-- Equation name is '~1297~1', location is LC1_A16, type is buried.
-- synthesized logic cell 
_LC1_A16 = LCELL( _EQ054);
  _EQ054 = !_LC1_A20 & !_LC2_A20;

-- Node name is ':1301' 
-- Equation name is '_LC7_A22', type is buried 
_LC7_A22 = LCELL( _EQ055);
  _EQ055 =  _LC5_A20
         # !_LC4_A24
         #  _LC6_A22 &  _LC7_A18;

-- Node name is ':1313' 
-- Equation name is '_LC8_A22', type is buried 
_LC8_A22 = LCELL( _EQ056);
  _EQ056 = !_LC3_A22 & !_LC4_A20 & !_LC7_A20 &  _LC7_A22;

-- Node name is ':1322' 
-- Equation name is '_LC5_A21', type is buried 
_LC5_A21 = LCELL( _EQ057);
  _EQ057 =  _LC1_A21 & !_LC2_A18
         #  _LC3_A20;

-- Node name is ':1331' 
-- Equation name is '_LC6_A21', type is buried 
_LC6_A21 = LCELL( _EQ058);
  _EQ058 = !_LC5_A18 &  _LC5_A21
         #  _LC1_A20
         #  _LC1_A18;

-- Node name is ':1340' 
-- Equation name is '_LC7_A21', type is buried 
_LC7_A21 = LCELL( _EQ059);
  _EQ059 = !_LC2_A20 &  _LC6_A21
         # !_LC4_A24;

-- Node name is ':1355' 
-- Equation name is '_LC1_A21', type is buried 
_LC1_A21 = LCELL( _EQ060);
  _EQ060 = !_LC3_A22 & !_LC5_A20 &  _LC7_A21
         # !_LC2_A13 & !_LC3_A22;

-- Node name is '~1370~1' 
-- Equation name is '~1370~1', location is LC3_A18, type is buried.
-- synthesized logic cell 
_LC3_A18 = LCELL( _EQ061);
  _EQ061 =  _LC1_A18
         #  _LC5_A18;

-- Node name is ':1370' 
-- Equation name is '_LC5_A16', type is buried 
_LC5_A16 = LCELL( _EQ062);
  _EQ062 =  _LC2_A16 & !_LC3_A20
         #  _LC2_A18 & !_LC3_A20
         #  _LC3_A18;

-- Node name is ':1379' 
-- Equation name is '_LC6_A16', type is buried 
_LC6_A16 = LCELL( _EQ063);
  _EQ063 = !_LC1_A20 &  _LC5_A16
         #  _LC2_A24
         #  _LC2_A20;

-- Node name is ':1388' 
-- Equation name is '_LC7_A16', type is buried 
_LC7_A16 = LCELL( _EQ064);
  _EQ064 = !_LC1_A24 &  _LC6_A16
         #  _LC4_A20
         #  _LC5_A20;

-- Node name is ':1397' 
-- Equation name is '_LC2_A16', type is buried 
_LC2_A16 = LCELL( _EQ065);
  _EQ065 = !_LC6_A20 &  _LC7_A16 & !_LC7_A20
         # !_LC6_A20 &  _LC8_A20;

-- Node name is '~1418~1' 
-- Equation name is '~1418~1', location is LC1_A15, type is buried.
-- synthesized logic cell 
!_LC1_A15 = _LC1_A15~NOT;
_LC1_A15~NOT = LCELL( _EQ066);
  _EQ066 = !_LC4_A18 & !_LC5_A18 &  _LC7_A18;

-- Node name is ':1439' 
-- Equation name is '_LC6_A23', type is buried 
_LC6_A23 = LCELL( _EQ067);
  _EQ067 = !_LC2_A22 &  _LC6_A23 &  _LC7_A23
         #  _LC1_A15 & !_LC2_A22 &  _LC7_A23;

-- Node name is '~1441~1' 
-- Equation name is '~1441~1', location is LC1_A13, type is buried.
-- synthesized logic cell 
_LC1_A13 = LCELL( _EQ068);
  _EQ068 = !_LC7_A20 & !_LC8_A20;



Project Information                          d:\vhdl\songer-03_24\tonetaba.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 14,684K