dds.hier_info

直接数字频率合成器

|dds
sinvalue[0] <= lpm_rom0:inst3.q[0]
sinvalue[1] <= lpm_rom0:inst3.q[1]
sinvalue[2] <= lpm_rom0:inst3.q[2]
sinvalue[3] <= lpm_rom0:inst3.q[3]
sinvalue[4] <= lpm_rom0:inst3.q[4]
sinvalue[5] <= lpm_rom0:inst3.q[5]
sinvalue[6] <= lpm_rom0:inst3.q[6]
sinvalue[7] <= lpm_rom0:inst3.q[7]
sinvalue[8] <= lpm_rom0:inst3.q[8]
sinvalue[9] <= lpm_rom0:inst3.q[9]
clk => lpm_rom0:inst3.inclock
clk => lpm_dff1:inst.clock
phase[0] => lpm_add_sub0:inst4.dataa[0]
phase[1] => lpm_add_sub0:inst4.dataa[1]
phase[2] => lpm_add_sub0:inst4.dataa[2]
phase[3] => lpm_add_sub0:inst4.dataa[3]
phase[4] => lpm_add_sub0:inst4.dataa[4]
phase[5] => lpm_add_sub0:inst4.dataa[5]
phase[6] => lpm_add_sub0:inst4.dataa[6]
phase[7] => lpm_add_sub0:inst4.dataa[7]
phase[8] => lpm_add_sub0:inst4.dataa[8]
freword[0] => lpm_add_sub0:inst6.dataa[0]
freword[1] => lpm_add_sub0:inst6.dataa[1]
freword[2] => lpm_add_sub0:inst6.dataa[2]
freword[3] => lpm_add_sub0:inst6.dataa[3]
freword[4] => lpm_add_sub0:inst6.dataa[4]
freword[5] => lpm_add_sub0:inst6.dataa[5]
freword[6] => lpm_add_sub0:inst6.dataa[6]
freword[7] => lpm_add_sub0:inst6.dataa[7]
freword[8] => lpm_add_sub0:inst6.dataa[8]


|dds|lpm_rom0:inst3
address[0] => address[0]~8.IN1
address[1] => address[1]~7.IN1
address[2] => address[2]~6.IN1
address[3] => address[3]~5.IN1
address[4] => address[4]~4.IN1
address[5] => address[5]~3.IN1
address[6] => address[6]~2.IN1
address[7] => address[7]~1.IN1
address[8] => address[8]~0.IN1
inclock => inclock~0.IN1
q[0] <= lpm_rom:lpm_rom_component.q
q[1] <= lpm_rom:lpm_rom_component.q
q[2] <= lpm_rom:lpm_rom_component.q
q[3] <= lpm_rom:lpm_rom_component.q
q[4] <= lpm_rom:lpm_rom_component.q
q[5] <= lpm_rom:lpm_rom_component.q
q[6] <= lpm_rom:lpm_rom_component.q
q[7] <= lpm_rom:lpm_rom_component.q
q[8] <= lpm_rom:lpm_rom_component.q
q[9] <= lpm_rom:lpm_rom_component.q


|dds|lpm_rom0:inst3|lpm_rom:lpm_rom_component
address[0] => altrom:srom.address[0]
address[1] => altrom:srom.address[1]
address[2] => altrom:srom.address[2]
address[3] => altrom:srom.address[3]
address[4] => altrom:srom.address[4]
address[5] => altrom:srom.address[5]
address[6] => altrom:srom.address[6]
address[7] => altrom:srom.address[7]
address[8] => altrom:srom.address[8]
inclock => altrom:srom.clocki
outclock => ~NO_FANOUT~
memenab => otri[9].OE
memenab => otri[8].OE
memenab => otri[7].OE
memenab => otri[6].OE
memenab => otri[5].OE
memenab => otri[4].OE
memenab => otri[3].OE
memenab => otri[2].OE
memenab => otri[1].OE
memenab => otri[0].OE
q[0] <= otri[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= otri[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= otri[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= otri[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= otri[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= otri[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= otri[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= otri[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= otri[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= otri[9].DB_MAX_OUTPUT_PORT_TYPE


|dds|lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom
address[0] => segment[0][9].WADDR
address[0] => segment[0][9].RADDR
address[0] => segment[0][8].WADDR
address[0] => segment[0][8].RADDR
address[0] => segment[0][7].WADDR
address[0] => segment[0][7].RADDR
address[0] => segment[0][6].WADDR
address[0] => segment[0][6].RADDR
address[0] => segment[0][5].WADDR
address[0] => segment[0][5].RADDR
address[0] => segment[0][4].WADDR
address[0] => segment[0][4].RADDR
address[0] => segment[0][3].WADDR
address[0] => segment[0][3].RADDR
address[0] => segment[0][2].WADDR
address[0] => segment[0][2].RADDR
address[0] => segment[0][1].WADDR
address[0] => segment[0][1].RADDR
address[0] => segment[0][0].WADDR
address[0] => segment[0][0].RADDR
address[1] => segment[0][9].WADDR1
address[1] => segment[0][9].RADDR1
address[1] => segment[0][8].WADDR1
address[1] => segment[0][8].RADDR1
address[1] => segment[0][7].WADDR1
address[1] => segment[0][7].RADDR1
address[1] => segment[0][6].WADDR1
address[1] => segment[0][6].RADDR1
address[1] => segment[0][5].WADDR1
address[1] => segment[0][5].RADDR1
address[1] => segment[0][4].WADDR1
address[1] => segment[0][4].RADDR1
address[1] => segment[0][3].WADDR1
address[1] => segment[0][3].RADDR1
address[1] => segment[0][2].WADDR1
address[1] => segment[0][2].RADDR1
address[1] => segment[0][1].WADDR1
address[1] => segment[0][1].RADDR1
address[1] => segment[0][0].WADDR1
address[1] => segment[0][0].RADDR1
address[2] => segment[0][9].WADDR2
address[2] => segment[0][9].RADDR2
address[2] => segment[0][8].WADDR2
address[2] => segment[0][8].RADDR2
address[2] => segment[0][7].WADDR2
address[2] => segment[0][7].RADDR2
address[2] => segment[0][6].WADDR2
address[2] => segment[0][6].RADDR2
address[2] => segment[0][5].WADDR2
address[2] => segment[0][5].RADDR2
address[2] => segment[0][4].WADDR2
address[2] => segment[0][4].RADDR2
address[2] => segment[0][3].WADDR2
address[2] => segment[0][3].RADDR2
address[2] => segment[0][2].WADDR2
address[2] => segment[0][2].RADDR2
address[2] => segment[0][1].WADDR2
address[2] => segment[0][1].RADDR2
address[2] => segment[0][0].WADDR2
address[2] => segment[0][0].RADDR2
address[3] => segment[0][9].WADDR3
address[3] => segment[0][9].RADDR3
address[3] => segment[0][8].WADDR3
address[3] => segment[0][8].RADDR3
address[3] => segment[0][7].WADDR3
address[3] => segment[0][7].RADDR3
address[3] => segment[0][6].WADDR3
address[3] => segment[0][6].RADDR3
address[3] => segment[0][5].WADDR3
address[3] => segment[0][5].RADDR3
address[3] => segment[0][4].WADDR3
address[3] => segment[0][4].RADDR3
address[3] => segment[0][3].WADDR3
address[3] => segment[0][3].RADDR3
address[3] => segment[0][2].WADDR3
address[3] => segment[0][2].RADDR3
address[3] => segment[0][1].WADDR3
address[3] => segment[0][1].RADDR3
address[3] => segment[0][0].WADDR3
address[3] => segment[0][0].RADDR3
address[4] => segment[0][9].WADDR4
address[4] => segment[0][9].RADDR4
address[4] => segment[0][8].WADDR4
address[4] => segment[0][8].RADDR4
address[4] => segment[0][7].WADDR4
address[4] => segment[0][7].RADDR4
address[4] => segment[0][6].WADDR4
address[4] => segment[0][6].RADDR4
address[4] => segment[0][5].WADDR4
address[4] => segment[0][5].RADDR4
address[4] => segment[0][4].WADDR4
address[4] => segment[0][4].RADDR4
address[4] => segment[0][3].WADDR4
address[4] => segment[0][3].RADDR4
address[4] => segment[0][2].WADDR4
address[4] => segment[0][2].RADDR4
address[4] => segment[0][1].WADDR4
address[4] => segment[0][1].RADDR4
address[4] => segment[0][0].WADDR4
address[4] => segment[0][0].RADDR4
address[5] => segment[0][9].WADDR5
address[5] => segment[0][9].RADDR5
address[5] => segment[0][8].WADDR5
address[5] => segment[0][8].RADDR5
address[5] => segment[0][7].WADDR5
address[5] => segment[0][7].RADDR5
address[5] => segment[0][6].WADDR5
address[5] => segment[0][6].RADDR5
address[5] => segment[0][5].WADDR5
address[5] => segment[0][5].RADDR5
address[5] => segment[0][4].WADDR5
address[5] => segment[0][4].RADDR5
address[5] => segment[0][3].WADDR5
address[5] => segment[0][3].RADDR5
address[5] => segment[0][2].WADDR5
address[5] => segment[0][2].RADDR5
address[5] => segment[0][1].WADDR5
address[5] => segment[0][1].RADDR5
address[5] => segment[0][0].WADDR5
address[5] => segment[0][0].RADDR5
address[6] => segment[0][9].WADDR6
address[6] => segment[0][9].RADDR6
address[6] => segment[0][8].WADDR6
address[6] => segment[0][8].RADDR6
address[6] => segment[0][7].WADDR6
address[6] => segment[0][7].RADDR6
address[6] => segment[0][6].WADDR6
address[6] => segment[0][6].RADDR6
address[6] => segment[0][5].WADDR6
address[6] => segment[0][5].RADDR6
address[6] => segment[0][4].WADDR6
address[6] => segment[0][4].RADDR6
address[6] => segment[0][3].WADDR6
address[6] => segment[0][3].RADDR6
address[6] => segment[0][2].WADDR6
address[6] => segment[0][2].RADDR6
address[6] => segment[0][1].WADDR6
address[6] => segment[0][1].RADDR6
address[6] => segment[0][0].WADDR6
address[6] => segment[0][0].RADDR6
address[7] => segment[0][9].WADDR7
address[7] => segment[0][9].RADDR7
address[7] => segment[0][8].WADDR7
address[7] => segment[0][8].RADDR7
address[7] => segment[0][7].WADDR7
address[7] => segment[0][7].RADDR7
address[7] => segment[0][6].WADDR7
address[7] => segment[0][6].RADDR7
address[7] => segment[0][5].WADDR7
address[7] => segment[0][5].RADDR7
address[7] => segment[0][4].WADDR7
address[7] => segment[0][4].RADDR7
address[7] => segment[0][3].WADDR7
address[7] => segment[0][3].RADDR7
address[7] => segment[0][2].WADDR7
address[7] => segment[0][2].RADDR7
address[7] => segment[0][1].WADDR7
address[7] => segment[0][1].RADDR7
address[7] => segment[0][0].WADDR7
address[7] => segment[0][0].RADDR7
address[8] => segment[0][9].WADDR8
address[8] => segment[0][9].RADDR8
address[8] => segment[0][8].WADDR8
address[8] => segment[0][8].RADDR8
address[8] => segment[0][7].WADDR8
address[8] => segment[0][7].RADDR8
address[8] => segment[0][6].WADDR8
address[8] => segment[0][6].RADDR8
address[8] => segment[0][5].WADDR8
address[8] => segment[0][5].RADDR8
address[8] => segment[0][4].WADDR8
address[8] => segment[0][4].RADDR8
address[8] => segment[0][3].WADDR8
address[8] => segment[0][3].RADDR8
address[8] => segment[0][2].WADDR8
address[8] => segment[0][2].RADDR8
address[8] => segment[0][1].WADDR8
address[8] => segment[0][1].RADDR8
address[8] => segment[0][0].WADDR8
address[8] => segment[0][0].RADDR8
clocki => segment[0][9].CLK0
clocki => segment[0][8].CLK0
clocki => segment[0][7].CLK0
clocki => segment[0][6].CLK0
clocki => segment[0][5].CLK0
clocki => segment[0][4].CLK0
clocki => segment[0][3].CLK0
clocki => segment[0][2].CLK0
clocki => segment[0][1].CLK0
clocki => segment[0][0].CLK0
clocko => ~NO_FANOUT~
q[0] <= segment[0][0].DATAOUT
q[1] <= segment[0][1].DATAOUT
q[2] <= segment[0][2].DATAOUT
q[3] <= segment[0][3].DATAOUT
q[4] <= segment[0][4].DATAOUT
q[5] <= segment[0][5].DATAOUT
q[6] <= segment[0][6].DATAOUT
q[7] <= segment[0][7].DATAOUT
q[8] <= segment[0][8].DATAOUT
q[9] <= segment[0][9].DATAOUT


|dds|lpm_add_sub0:inst4
dataa[0] => dataa[0]~8.IN1
dataa[1] => dataa[1]~7.IN1
dataa[2] => dataa[2]~6.IN1
dataa[3] => dataa[3]~5.IN1