dds.tan.rpt

直接数字频率合成器

+------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------+-------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPF10K10LC84-3     ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                            ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------+-------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                          ; To                                                                ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------+-------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 96.15 MHz ( period = 10.400 ns )                    ; lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[0] ; lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[7]                     ; clk        ; clk      ; None                        ; None                      ; 8.200 ns                ;
; N/A                                     ; 98.04 MHz ( period = 10.200 ns )                    ; lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[2] ; lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra8 ; clk        ; clk      ; None                        ; None                      ; 7.800 ns                ;
; N/A                                     ; 98.04 MHz ( period = 10.200 ns )                    ; lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[2] ; lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra8 ; clk        ; clk      ; None                        ; None                      ; 7.800 ns                ;
; N/A                                     ; 98.04 MHz ( period = 10.200 ns )                    ; lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[2] ; lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra8 ; clk        ; clk      ; None                        ; None                      ; 7.800 ns                ;
; N/A                                     ; 98.04 MHz ( period = 10.200 ns )                    ; lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[2] ; lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra8 ; clk        ; clk      ; None                        ; None                      ; 7.800 ns                ;
; N/A                                     ; 98.04 MHz ( period = 10.200 ns )                    ; lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[2] ; lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra8 ; clk        ; clk      ; None                        ; None                      ; 7.800 ns                ;
; N/A                                     ; 98.04 MHz ( period = 10.200 ns )                    ; lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[2] ; lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra8 ; clk        ; clk      ; None                        ; None                      ; 7.800 ns                ;
; N/A                                     ; 98.04 MHz ( period = 10.200 ns )                    ; lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[2] ; lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra8 ; clk        ; clk      ; None                        ; None                      ; 7.800 ns                ;
; N/A                                     ; 98.04 MHz ( period = 10.200 ns )                    ; lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[1] ; lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[7]                     ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 98.04 MHz ( period = 10.200 ns )                    ; lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[0] ; lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[6]                     ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 98.04 MHz ( period = 10.200 ns )                    ; lpm_dff1:inst|lpm_ff:lpm_ff_component|dffs[2] ; lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[9]~reg_ra8 ; clk        ; clk      ; None                        ; None                      ; 7.800 ns                ;